Avago-technologies LSI8751D Manuel d'utilisateur

®DB14-000165-01LSI53C875/875EPCI to Ultra SCSII/O ProcessorTECHNICALMANUALApril 2003Version 4.2

x ContentsIndexCustomer FeedbackFigures1.1 LSI53C875 External Memory Interface 1-21.2 LSI53C875 Chip Block Diagram 1-32.1 DMA FIFO Sections 2-152.2 LS

4-8 Signal DescriptionsTable 4.3 describes the LSI53C875JB and LSI53C875JBE Power andGround Signals group.Table 4.3 LSI53C875JB and LSI53C875JBE Power

4-9Figure 4.5 is the functional signal grouping for the LSI53C875.Figure 4.5 LSI53C875 Functional Signal GroupingLSI53C875CLKRSTAD[31:0]C_BE[3:0]/PARF

4-10 Signal DescriptionsTable 4.4 describes the System Signals group.Table 4.4 System SignalsNamePin No.LSI53C875,LSI53C875J,LSI53C875N,LSI53C875JBTyp

4-11Table 4.5 describes the Address and Data Signals group.Table 4.5 Address and Data SignalsName Pin No.Type DescriptionAD[31:0] LSI53C875LSI53C875J:

4-12 Signal DescriptionsTable 4.6 describes the Interface Control Signals group.PAR LSI53C875,LSI53C875J: 25LSI53C875N: 31LSI53C875JB: H1T/S Parity is

4-13Table 4.7 describes the Arbitration Signals group.IRDY/ 17/23/F1 S/T/S Initiator Ready indicates the initiating agent’s (bus master’s)ability to c

4-14 Signal DescriptionsTable 4.8 describes the Error Reporting Signals group.Table 4.8 Error Reporting SignalsNamePin No.LSI53C875,LSI53C875J,LSI53C8

4-15Table 4.9 describes the SCSI Signals group.Table 4.9 SCSI SIgnalsNamePin No.LSI53C875,LSI53C875J,LSI53C875N,LSI53C875JB Type DescriptionSCLK 56/73

4-16 Signal DescriptionsSCTRL/ LSI53C875,LSI53C875J:92, 90, 95, 91,97, 98, 100,96, 94LSI53C875N:122, 120, 125,121, 127, 128,130, 126, 124LSI53C875JB:J

4-17SDIRP[1:0](SDIPR1 is notavailable onLSI53C875J,LSI53C875JB)130, 119; NA,119/171,149/NA, D10O Driver direction control for SCSI parity signals. In

Contents xi7.12 Operating Register/SCRIPTS RAM Write 7-187.13 External Memory Read 7-207.14 External Memory Write 7-227.15 Opcode Fetch, Nonburst 7-24

4-18 Signal DescriptionsTable 4.10 describes the Additional Interface Signals group.Table 4.10 Additional Interface SignalsNamePin No.LSI53C875,LSI53C

4-19GPIO[4:3] 71, 70/90,89/L9, M9I/O General Purpose I/O pins. GPIO4 powers up as an output.It can be used as the enable line for VPP, the 12 V powers

4-20 Signal DescriptionsBIG_LIT/ (Notavailable onLSI53C875J,LSI53C875JB)142,NA/184/NAI Big_Little Endian Select. When this pin is driven LOW,the LSI53

4-21Table 4.11 describes the External Memory Interface Signals group.Table 4.11 External Memory Interface SignalsNamePin No.LSI53C875,LSI53C875J,LSI53

4-22 Signal DescriptionsTable 4.12 describes the JTAG Signals group for the LSI53C875J,LSI53C875N, and LSI53C875JB.4.1 MAD Bus ProgrammingThe MAD[7:0]

MAD Bus Programming 4-23• MAD[6] Subsystem Data configuration. Refer to Table 4.13 andTable 4.14 for the different configurations.• MAD[5] SCRIPTS RAM d

4-24 Signal Descriptions• MAD[0] Slow ROM pin. When pulled down, it enables two extraclock cycles of data access time to allow use of slower memorydev

LSI53C875/875E PCI to Ultra SCSI I/O Processor 5-1Chapter 5SCSI OperatingRegistersThis section contains descriptions of all LSI53C875 operating regist

5-2 SCSI Operating Registers.Table 5.1 LSI53C875 Register Map31 16 15 0 Mem I/O ConfigSCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00 0x80GPREG SDID SXFER SCID 0x04 0

5-3Register: 0x00 (0x80)SCSI Control Zero (SCNTL0)Read/WriteARB1[1:0] Arbitration Mode Bits 1 and 0 [7:6]Simple Arbitration1. The LSI53C875 waits for

xii ContentsTables2.1 External Memory Support 2-72.2 Bits Used for Parity Control and Generation 2-132.3 SCSI Parity Control 2-142.4 SCSI Parity Error

5-4 SCSI Operating Registers2. It asserts SBSY/ and its SCSI ID (the highest priorityID stored in the SCSI Chip ID (SCID) register) onto theSCSI bus.3

5-5time-out occurs while attempting to select a target device,SATN/ is deasserted at the same time SSEL/ isdeasserted. When this bit is cleared, the S

5-6 SCSI Operating RegistersTRG Target Mode 0This bit determines the default operating mode of theLSI53C875. The user must manually set the target ori

5-7DHP Disable Halt on Parity Error or ATN (Target Only) 5The DHP bit is only defined for target mode. When thisbit is cleared, the LSI53C875 halts the

5-8 SCSI Operating RegistersIARB Immediate Arbitration 1Setting this bit causes the SCSI core to immediatelybegin arbitration once a Bus Free phase is

5-9The determination of whether the transfer is a send orreceive is made according to the value written to the I/Obit in SCSI Output Control Latch (SO

5-10 SCSI Operating Registersodd byte boundary, the LSI53C875 stores the last byte inthe SCSI Wide Residue (SWIDE) register during areceive operation,

5-11VUE1 Vendor Unique Enhancements Bit 1 1This bit is used to disable the automatic byte count reloadduring Block Move instructions in the command ph

5-12 SCSI Operating RegistersRegister: 0x03 (0x83)SCSI Control Three (SCNTL3)Read/WriteULTRA Ultra Enable 7Setting this bit enables Ultra SCSI synchro

5-13at a time, with the least significant byte on SD[7:0]/, SDP/and the most significant byte on SD[15:8]/, SDP1/.Command, Status, and Message phases ar

Contents xiii7.1 Absolute Maximum Stress Ratings 7-27.2 Operating Conditions 7-27.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 7-37.4 SCSI Signal

5-14 SCSI Operating RegistersIf the SCSI clock doubler is enabled, use the desiredfrequency after doubling to determine the conversionfactor.Register:

5-15Register: 0x05 (0x85)SCSI Transfer (SXFER)Read/WriteNote: When using Table Indirect I/O commands, bits [7:0] of thisregister are loaded from the I

5-16 SCSI Operating RegistersThe LSI53C875 is connected to a hard disk which cantransfer data at 10 Mbytes/s synchronously. TheLSI53C875’s SCLK is run

5-17MO[4:0] Max SCSI Synchronous Offset [4:0]These bits describe the maximum SCSI synchronousoffset used by the LSI53C875 when transferringsynchronous

5-18 SCSI Operating RegistersRegister: 0x06 (0x86)SCSI Destination ID (SDID)Read/WriteR Reserved [7:4]ENC[3:0] Encoded Destination SCSI ID [3:0]Writin

5-19register. The SCSI ID is defined by the user in aSCRIPTS select or reselect instruction. The value writtenshould be the binary-encoded ID value. Th

5-20 SCSI Operating Registerssoftware drives this pin low to turn on the LED, or drives it high to turnoff the LED.SDMS software uses the GPIO[1:0] pi

5-21Register: 0x09 (0x89)SCSI Output Control Latch (SOCL)Read/WriteREQ Assert SCSI REQ/ Signal 7ACK Assert SCSI ACK/ Signal 6BSY Assert SCSI BSY/ Sign

5-22 SCSI Operating RegistersRegister: 0x0A (0x09)SCSI Selector ID (SSID)Read OnlyVAL SCSI Valid 7If VAL is asserted, then the two SCSI IDs are detect

5-23MSG SMSG/ Status 2C/D SC_D/ Status 1I/O SI_O/ Status 0This register returns the SCSI control line status. A bit is set when thecorresponding SCSI

xiv Contents7.29 Ultra SCSI Differential Transfers 20.0 Mbytes/s(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),80 MHz Clock 7-57A.1 Configuratio

5-24 SCSI Operating RegistersMDPE Master Data Parity Error 6This bit is set when the LSI53C875 as a master detectsa data parity error, or a target dev

5-25• A Block Move instruction is executed with 0x000000loaded into the DMA Byte Counter (DBC) register,indicating that there are zero bytes to move.•

5-26 SCSI Operating RegistersRegister: 0x0D (0x8D)SCSI Status Zero (SSTAT0)Read OnlyILF SIDL Least Significant Byte Full 7This bit is set when the leas

5-27AIP Arbitration in Progress 4Arbitration in Progress (AIP = 1) indicates that theLSI53C875 has detected a Bus Free condition, assertedBSY, and ass

5-28 SCSI Operating RegistersSDP0L Latched SCSI Parity 3This bit reflects the SCSI parity signal (SDP0/),corresponding to the data latched in the SCSI

5-29Register: 0x0F (0x8F)SCSI Status Two (SSTAT2)Read OnlyILF1 SIDL Most Significant Byte Full 7This bit is set when the most significant byte in the SC

5-30 SCSI Operating RegistersFF4 FIFO Flags bit 4 4This is the most significant bit in the SCSI FIFO Flagsfield, with the rest of the bits in SCSI Statu

5-31Registers:0x10–0x13 (0x90–0x93)Data Structure Address (DSA)Read/WriteDSA Data Structure Address [31:0]This 32-bit register contains the base addre

5-32 SCSI Operating Registers2. Wait for an interrupt.3. Read the Interrupt Status (ISTAT) register.4. If the SCSI Interrupt Pending bit is set, then

5-33notify an external processor of a predefined conditionwhile SCRIPTS are running. The external processor mayalso notify the LSI53C875 of a predefined

LSI53C875/875E PCI to Ultra SCSI I/O Processor 1-1Chapter 1General DescriptionChapter 1 is divided into the following sections:• Section 1.1, “Package

5-34 SCSI Operating Registers• The LSI53C875 is reselected• A SCSI gross error occurs• An unexpected disconnect occurs• A SCSI reset occurs• A parity

5-35Register: 0x19 (0x99)Chip Test One (CTEST1)Read OnlyFMT[3:0] Byte Empty in DMA FIFO [7:4]These bits identify the bottom bytes in the DMA FIFO that

5-36 SCSI Operating RegistersSIGP Signal Process 6This bit is a copy of the SIGP bit in the Interrupt Status(ISTAT) register (bit 5). The SIGP bit is

5-37DREQ Data Request Status 1This bit indicates the status of the LSI53C875’s internalData Request signal (DREQ). When this bit is set, DREQis active

5-38 SCSI Operating RegistersFM Fetch Pin Mode 1When set, this bit causes the FETCH/ pin to deassertduring indirect and table indirect read operations

5-39Register: 0x20 (0xA0)DMA FIFO (DFIFO)Read/WriteBO[7:0] Byte Offset Counter [7:0]These bits, along with bits [1:0] in the Chip Test Five(CTEST5) re

5-40 SCSI Operating Registers3. If the DMA FIFO size is set to 88 bytes, and theresult with 0x7F for a byte count between 0 and 64.If the DMA FIFO siz

5-41the shadow copies STEMP (Shadow TEMP) and SDSA(Shadow DSA). The registers are shadowed to preventthem from being overwritten during a Memory-to-Me

5-42 SCSI Operating RegistersRegister: 0x22 (0xA2)Chip Test Five (CTEST5)Read/WriteADCK Clock Address Incrementor 7Setting this bit increments the add

5-43the DMAWR signal indicates that data is transferred fromthe SCSI bus to the host bus. Deasserting the DMAWRsignal transfers data from the host bus

1-2 General DescriptionThe LSI53C875 is a pin-for-pin replacement for the LSI53C825 PCI toSCSI I/O processor, with added support for the SCSI-3 Ultra

5-44 SCSI Operating RegistersRegisters:0x24–0x26 (0xA4–0xA6)DMA Byte Counter (DBC)Read/WriteDBC DMA Byte Counter [23:0]This 24-bit register determines

5-45Register: 0x27 (0xA7)DMA Command (DCMD)Read/WriteDCMD DMA Command [7:0]This 8-bit register determines the instruction for theLSI53C875 to execute.

5-46 SCSI Operating RegistersRegisters:0x2C–0x2F (0xAC–0xAF)DMA SCRIPTS Pointer (DSP)Read/WriteDSP DMA SCRIPTS Pointer [31:0]To execute SCSI SCRIPTS,

5-47Registers:0x34–0x37 (0xB4–0xB7)Scratch Register A (SCRATCHA)Read/WriteSCRATCHA Scratch Register A [31:0]This is a general purpose, user-definable s

5-48 SCSI Operating Registersset in BL[1:0]) during normal operation. The fairnessdelay is not inserted during PCI retry cycles. This givesthe CPU and

5-49ERL Enable Read Line 3This bit enables a PCI Read Line command. If PCI cachemode is enabled by setting bits in the PCI Cache LineSize register, th

5-50 SCSI Operating RegistersRegister: 0x39 (0xB9)DMA Interrupt Enable (DIEN)Read/WriteR Reserved 7MDPE Master Data Parity Error 6BF Bus Fault 5ABRT A

5-51For more information on interrupts, see Chapter 2, “FunctionalDescription.”Register: 0x3A (0xBA)Scratch Byte Register (SBR)Read/WriteThis is a gen

5-52 SCSI Operating Registerscontinues fetching and executing instructions until aninterrupt condition occurs. For normal SCSI SCRIPTSoperation, keep

5-53COM LSI53C700 Family Compatibility 0When the COM bit is cleared, the LSI53C875 behaves ina manner compatible with the LSI53C700 family;selection/r

1-3A block diagram of the LSI53C875 is pictured in Figure 1.2.Figure 1.2 LSI53C875 Chip Block DiagramThe LSI53C875 integrates a high-performance SCSI

5-54 SCSI Operating RegistersM/A SCSI Phase Mismatch - Initiator Mode; 7SCSI ATN Condition - Target ModeIn initiator mode, this bit is set when the SC

5-55• Residual data in SCSI FIFO – starting a transfer otherthan synchronous data receive with data left in theSCSI synchronous receive FIFO.UDC Unexp

5-56 SCSI Operating RegistersR Reserved [7:3]STO Selection or Reselection Time-out 2The SCSI device which the LSI53C875 is attempting toselect or rese

5-57When performing consecutive 8-bit reads of the DMA Status (DSTAT),SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One(SIST1) registe

5-58 SCSI Operating Registers• Data Overflow – writing too many bytes to the SCSIFIFO, or the synchronous offset causes overwritingthe SCSI FIFO.• Offs

5-59Register: 0x43 (0xC3)SCSI Interrupt Status One (SIST1)Read OnlyReading the SCSI Interrupt Status One (SIST1) register returns thestatus of the var

5-60 SCSI Operating RegistersRegister: 0x44 (0xC4)SCSI Longitudinal Parity (SLPAR)Read/WriteSLPAR SCSI Longitudinal Parity [7:0]The SCSI Longitudinal

5-61A one in any bit position of the final SLPAR value would indicate atransmission error.The SCSI Longitudinal Parity (SLPAR) register is also used to

5-62 SCSI Operating RegistersWide Residue message is received. It may also be anoverrun data byte. The power-up value of this register isindeterminate

5-63Register: 0x47 (0xC7)General Purpose Pin Control (GPCNTL)Read/WriteThis register is used to determine if the pins controlled by the GeneralPurpose

1-4 General Description1.1 Package and Feature OptionsThe LSI53C875 is available in three versions with different packagingand feature options. The LS

5-64 SCSI Operating RegistersRegister: 0x48 (0xC8)SCSI Timer Zero (STIME0)Read/WriteHTH Handshake-to-Handshake Timer Period [7:4]These bits select the

5-65SEL Selection Time-Out [3:0]These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200 µs selection aborttime

5-66 SCSI Operating RegistersRegister: 0x49 (0xC9)SCSI Timer One (STIME1)Read/WriteR Reserved 7HTHBA Handshake-to-Handshake Timer Bus 6Activity Enable

5-67HTH [7:4]SEL [3:0]GEN [3:0]Minimum Time-out1(50 MHz Clock)1. These values will be correct if the CCF bits in the SCSI Control Three(SCNTL3) regist

5-68 SCSI Operating RegistersHTHSF Handshake-to-Handshake Timer Scale Factor 4Setting this bit causes this timer to shift by a factor of 16.GEN[3:0] G

5-69GEN bit in the SCSI Interrupt Status One (SIST1) registeris set. Refer to the table under SCSI Timer Zero(STIME0), bits [3:0], for the available t

5-70 SCSI Operating RegistersRegister: 0x4B (0xCB)Response ID One (RESPID1)Read/WriteRESPID1 Response ID One [15:8]RESPID0 and RESPID1 contain the sel

5-71SLT Selection Response Logic Test 3This bit is set when the LSI53C875 is ready to beselected or reselected. This does not take into accountthe bus

5-72 SCSI Operating RegistersRegister: 0x4D (0xCD)SCSI Test One (STEST1)Read/WriteSCLK SCSI Clock 7When set, this bit disables the external SCLK (SCSI

5-732. Wait 20 µs.3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI TestThree (STEST3), bit 5).4. Set the clock conversion factor using

TolerANT®Technology 1-51.3 TolerANT®TechnologyThe LSI53C875 features TolerANT technology, which includes activenegation on the SCSI drivers and input

5-74 SCSI Operating RegistersSLB SCSI Loopback Mode 4Setting this bit allows the LSI53C875 to perform SCSIloopback diagnostics. That is, it enables th

5-75set this bit for access to the SCSI bit-level registers SCSIOutput Data Latch (SODL), SCSI Bus Control Lines(SBCL), and input registers.Register:

5-76 SCSI Operating RegistersHSC Halt SCSI Clock 5Asserting this bit causes the internal divided SCSI clockto come to a stop in a glitchless manner. T

5-77SCSI Input Data Latch (SIDL), SCSI Output Data Latch(SODL), and SODR full bits in the SCSI Status Zero(SSTAT0) and SCSI Status Two (SSTAT2) are cl

5-78 SCSI Operating RegistersRegisters:0x54–0x55 (0xD4–0xD5)SCSI Output Data Latch (SODL)Read/WriteSODL SCSI Output Data Latch [15:0]This register is

5-79Registers:0x5C–0x5F (0xDC–0xDF)Scratch Register B (SCRATCHB)Read/WriteSCRATCHB Scratch Register B [31:0]This is a general purpose user definable sc

5-80 SCSI Operating Registers

LSI53C875/875E PCI to Ultra SCSI I/O Processor 6-1Chapter 6Instruction Set of theI/O ProcessorAfter power-up and initialization, the LSI53C875 can be

6-2 Instruction Set of the I/O Processorboundary since all SCRIPTS are 8 or 12 bytes long. Instructions arefetched until an interrupt instruction is e

SCSI SCRIPTS 6-3Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DCMD) and DMA ByteC

iiThis document contains proprietary information of LSI Logic Corporation. Theinformation contained herein is not to be used by or disclosed to third

1-6 General Description1.4 LSI53C875 Benefits SummaryThe section provides an overview of the LSI53C875 features andbenefits. It contains information on

6-4 Instruction Set of the I/O ProcessorThe process repeats until the internally stored byte count has reachedzero. The LSI53C875 releases the PCI bus

Block Move Instructions 6-56.2 Block Move InstructionsPerforming a Block Move instruction, bit 5, Source I/O - Memory Enable(SIOM) and bit 4, Destinat

6-6 Instruction Set of the I/O ProcessorOnce the data pointer address is loaded, it is executedas when the chip operates in the direct mode. Thisindir

Block Move Instructions 6-7Figure 6.2 Block Move Instruction RegisterPrior to the start of an I/O, the Data Structure Address(DSA) register should be

6-8 Instruction Set of the I/O ProcessorSCRIPTS can directly execute operating system I/O datastructures, saving time at the beginning of an I/Ooperat

Block Move Instructions 6-9overwrites the DMA Byte Counter (DBC) registerwith the length of the Command Descriptor Block:6, 10, or 12 bytes.– If the V

6-10 Instruction Set of the I/O ProcessorInitiator ModeThese instructions perform the following steps:1. The LSI53C875 verifies that it is connected to

Block Move Instructions 6-115. If the SCSI phase bits do not match the value storedin the SCSI Status One (SSTAT1) register, theLSI53C875 generates a

6-12 Instruction Set of the I/O Processorbytes transferred. In addition, the DMA Next Address(DNAD) register is incremented by the number of bytestran

I/O Instruction 6-13Target ModeReselect InstructionThe LSI53C875 arbitrates for the SCSI bus by assertingthe SCSI ID stored in the SCSI Chip ID (SCID)

LSI53C875 Benefits Summary 1-71.4.2 PCI PerformanceTo improve PCI performance, the LSI53C875:• Complies with PCI 2.1 specification.• Bursts 2, 4, 8, 16,

6-14 Instruction Set of the I/O ProcessorIf reselected, the LSI53C875 fetches the next instructionfrom the address pointed to by the 32-bit jump addre

I/O Instruction 6-15Figure 6.3 I/O Instruction Register31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1031 3029 28 2

6-16 Instruction Set of the I/O ProcessorInitiator ModeSelect InstructionThe LSI53C875 arbitrates for the SCSI bus by assertingthe SCSI ID stored in t

I/O Instruction 6-17Wait Reselect InstructionIf the LSI53C875 is selected before being reselected, itfetches the next instruction from the address poi

6-18 Instruction Set of the I/O ProcessorData Structure Address (DSA) register, and used as anoffset relative to the value in the Data Structure Addre

I/O Instruction 6-19DirectUses the device ID and physical address in theinstruction.Table IndirectUses the physical jump address, but fetches data usi

6-20 Instruction Set of the I/O ProcessorR Reserved [23:20]ENDID[3:0] Encoded SCSI Destination ID [19:16]This 4-bit field specifies the destination SCSI

Read/Write Instructions 6-21The Set/Clear SCSI ACK/ATN instruction is used aftermessage phase Block Move operations to give theInitiator the opportuni

6-22 Instruction Set of the I/O ProcessorO[2:0] Operator [26:24]These bits are used in conjunction with the opcode bitsto determine which instruction

Read/Write Instructions 6-23Figure 6.4 illustrates the Read/Write Instruction register.Figure 6.4 Read/Write Instruction Register31 3029 28 27 26 25 2

1-8 General Description• Compiler-compatible with existing LSI53C7XX and LSI53C8XXfamily SCRIPTS.• Direct connection to PCI, and SCSI SE and different

6-24 Instruction Set of the I/O Processor6.4.4 Move To/From SFBR CyclesAll operations are read-modify-writes. However, two registers areinvolved, one

Read/Write Instructions 6-25Miscellaneous Notes:˘ Substitute the desired register name or address for “RegA” in the syntax examples.˘ data8 indicates

6-26 Instruction Set of the I/O Processor6.5 Transfer Control Instructions6.5.1 First DwordIT[1:0] Instruction Type -Transfer Control Instruction [31:

Transfer Control Instructions 6-27Call InstructionThe LSI53C875 can do a true/false comparison of theALU carry bit, or compare the phase and/or data a

6-28 Instruction Set of the I/O ProcessorFigure 6.5 Transfer Control Instructions31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

Transfer Control Instructions 6-29Return InstructionThe LSI53C875 can do a true/false comparison of theALU carry bit, or compare the phase and/or data

6-30 Instruction Set of the I/O ProcessorTrue/False bit fields. If the comparisons are true, and theInterrupt-on-the-Fly bit is set (bit 2), the LSI53C

Transfer Control Instructions 6-31The SCRIPTS program counter is a 32-bit value pointingto the SCRIPT currently being executed by theLSI53C875. The ne

6-32 Instruction Set of the I/O ProcessorCD Compare Data 18When this bit is set, the first byte received from the SCSIdata bus (contained in SCSI First

Memory Move Instructions 6-33DCV Data Compare Value [7:0]This 8-bit field is the data to be compared against theregister. These bits are used in conjun

LSI53C875 Benefits Summary 1-91.4.6 ReliabilityThe following features enhance the reliability of the LSI53C875:• 2 kV ESD protection on SCSI signals.•

6-34 Instruction Set of the I/O ProcessorThe DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address(DSA) registers are additional holding register

Memory Move Instructions 6-35The SFBR is not writable using the CPU, and therefore not by a MemoryMove. However, it can be loaded using SCRIPTS Read/W

6-36 Instruction Set of the I/O ProcessorFigure 6.6 Memory Move Instruction31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5

Load and Store Instructions 6-376.7 Load and Store InstructionsThe Load and Store instructions provide a more efficient way to movedata from/to memory

6-38 Instruction Set of the I/O Processor6.7.1 First DwordIT[2:0] Instruction Type [31:29]These bits should be 111, indicating the Load and Storeinstr

Load and Store Instructions 6-39R Reserved 23RA[6:0] Register Address [22:16]A[6:0] selects the register to Load and Store to/fromwithin the LSI53C875

6-40 Instruction Set of the I/O ProcessorFigure 6.7 Load and Store Instruction Format31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

LSI53C875/875E PCI to Ultra SCSI I/O Processor 7-1Chapter 7Instruction Set of theI/O ProcessorThis chapter specifies the LSI53C875 electrical and mecha

7-2 Instruction Set of the I/O ProcessorTable 7.1 Absolute Maximum Stress RatingsSymbol Parameter Min Max Unit Test ConditionsTSTGStorage temperature

DC Characteristics 7-3Table 7.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/Symbol Parameter Min Max Unit Test ConditionsVIHInput high voltage 2.0

1-10 General Description

7-4 Instruction Set of the I/O ProcessorTable 7.6 CapacitanceSymbol Parameter Min Max Unit Test ConditionsCIInput capacitance of input pads – 7 pF –CI

DC Characteristics 7-5Table 7.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/, IRDY/, TRDY/,DEVSEL/, STOP/, PERR/, PARSymbol Parameter Min Max Un

7-6 Instruction Set of the I/O ProcessorTable 7.12 Bidirectional Signals—MAD[7:0]Symbol Parameter Min Max Unit Test ConditionsVIHInput high voltage 2.

TolerANT Technology Electrical Characteristics 7-77.2 TolerANT Technology Electrical CharacteristicsThe LSI53C875 features TolerANT technology, which

7-8 Instruction Set of the I/O ProcessorFigure 7.1 Rise and Fall Time Test ConditionsFigure 7.2 SCSI Input FilteringESD Electrostatic discharge 2 – kV

TolerANT Technology Electrical Characteristics 7-9Figure 7.3 Hysteresis of SCSI ReceiverFigure 7.4 Input Current as a Function of Input Voltage1Receiv

7-10 Instruction Set of the I/O ProcessorFigure 7.5 Output Current as Function of Output Voltage7.3 AC CharacteristicsThe AC characteristics described

AC Characteristics 7-11Figure 7.6 Clock WaveformsTable 7.16 Clock TimingSymbol Parameter Min Max Unitt1Bus clock cycle time 30 DC nsSCSI clock cycle t

7-12 Instruction Set of the I/O ProcessorTable 7.17 and Figure 7.7 provide Reset Input timing data.Figure 7.7 Reset InputTable 7.17 Reset InputSymbol

PCI and External Memory Interface Timing Diagrams 7-13Table 7.18 and Figure 7.8 provide Interrupt Output timing data.Figure 7.8 Interrupt Output7.4 PC

LSI53C875/875E PCI to Ultra SCSI I/O Processor 2-1Chapter 2Functional DescriptionChapter 2 is divided into the following sections:• Section 2.1, “SCSI

7-14 Instruction Set of the I/O ProcessorTiming diagrams included in this section are:• Target Timing– PCI Configuration Register Read– PCI Configuratio

PCI and External Memory Interface Timing Diagrams 7-157.4.1 Target TimingFigure 7.9 through Figure 7.14 describe Target timing.Figure 7.9 PCI Configura

7-16 Instruction Set of the I/O ProcessorFigure 7.10 PCI Configuration Register WriteData InByte EnableAddr Int2t1t2t1t2t1t1t2t2t3t2t1t3t2t1CLK(Driven

PCI and External Memory Interface Timing Diagrams 7-17Figure 7.11 Operating Register/SCRIPTS RAM ReadDataByte EnableAddr Int2t1t2t1t2t1t1t2t2t3t2t1t3C

7-18 Instruction Set of the I/O ProcessorFigure 7.12 Operating Register/SCRIPTS RAM WriteByte EnableAddr InCMDt2t1t2t1t2t1t1t2t2t3t2t1t3CLK(Driven by

PCI and External Memory Interface Timing Diagrams 7-19This page intentionally left blank.

7-20 Instruction Set of the I/O ProcessorFigure 7.13 External Memory Readt12CLK(Driven by System)PAR(Driven by Master-Addr;IRDY/(Driven by Master)TRDY

PCI and External Memory Interface Timing Diagrams 7-21Figure 7.13 External Memory Read (Cont.)CLK(Driven by System)PAR(Driven by Master-Addr;IRDY/(Dri

7-22 Instruction Set of the I/O ProcessorFigure 7.14 External Memory WriteCLK(Driven by System)PAR(Driven by Master-Addr;IRDY/(Driven by Master)TRDY/(

PCI and External Memory Interface Timing Diagrams 7-23Figure 7.14 External Memory Write (Cont.)11 12 13 14 15 16 17 18 19 20t2t221t1t3t3Data InByte En

2-2 Functional DescriptionThe SCSI core offers low level register access or a high level controlinterface. Like first generation SCSI devices, the LSI5

7-24 Instruction Set of the I/O Processor7.4.2 Initiator TimingFigure 7.17 through Figure 7.20 describe LSI53C875 Initiator timing.Figure 7.15 Opcode

PCI and External Memory Interface Timing Diagrams 7-25Figure 7.16 Burst Opcode FetchCLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAME/C_BE/PAR/(Driven by Syst

7-26 Instruction Set of the I/O ProcessorFigure 7.17 Back-to-Back Readt1CLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAME/C_BE/PAR/(Driven by System)(Driven b

PCI and External Memory Interface Timing Diagrams 7-27Figure 7.18 Back-to-Back WriteAddrOutCLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAME/C_BE/PAR/(Driven

7-28 Instruction Set of the I/O ProcessorFigure 7.19 Burst Read123456789t9CLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAME/C_BE/PAR/(Driven by LSI53C875)(Dri

PCI and External Memory Interface Timing Diagrams 7-29Figure 7.19 Burst Read (Cont.)10 11 12 13 14 15 16 17 18CLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAM

7-30 Instruction Set of the I/O ProcessorFigure 7.20 Burst Writet3t3123456789t9CLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRAME/C_BE/PAR/(Driven by LSI53C875

PCI and External Memory Interface Timing Diagrams 7-31Figure 7.20 Burst Write (Cont.)10 11 12 13 14 15 16 17 18CLKGPIO0_FETCH/GPIO1_MASTER/REQ/GNT/FRA

7-32 Instruction Set of the I/O Processor7.4.3 External Memory TimingFigure 7.21 through Figure 7.30 describe LSI53C875 External Memorytiming.Figure 7

PCI and External Memory Interface Timing Diagrams 7-33Figure 7.21 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes), Single Byte Access(Cont.)t17CLKMAD(Add

SCSI Functional Description 2-3or SCSI-3 logical bus definitions without sacrificing I/O performance.SCSI SCRIPTS are hardware independent, so they can

7-34 Instruction Set of the I/O ProcessorFigure 7.22 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes), Single Byte AccessCLKMAD(Driven by LSI53C875)MAS2/

PCI and External Memory Interface Timing Diagrams 7-35Figure 7.22 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes), Single Byte Access(Cont.)t23CLKMAD(Dr

7-36 Instruction Set of the I/O ProcessorFigure 7.23 Read Cycle, Normal/Fast Memory (≥ 64 Kbyte), Multiple Byte Access12345678910111213141516CLK(Drive

PCI and External Memory Interface Timing Diagrams 7-37Figure 7.23 Read Cycle, Normal/Fast Memory (≥ 64 Kbyte), Multiple Byte Access(Cont.)17 18 19 20

7-38 Instruction Set of the I/O ProcessorFigure 7.24 Write Cycle, Normal/Fast Memory (≥ 64 Kbyte), Multiple Byte Access12345678910111213141516CLK(Driv

PCI and External Memory Interface Timing Diagrams 7-39Figure 7.24 Write Cycle, Normal/Fast Memory (≥ 64 Kbyte), Multiple Byte Access(Cont.)17 18 19 20

7-40 Instruction Set of the I/O ProcessorFigure 7.25 Read Cycle, Slow Memory (≥ 64 Kbyte)MAD(Address driven by LSI53C875Data driven by memory)MAS2/(Dr

PCI and External Memory Interface Timing Diagrams 7-41Figure 7.25 Read Cycle, Slow Memory (≥ 64 Kbyte) (Cont.)MAD(Address driven by LSI53C875Data driv

7-42 Instruction Set of the I/O ProcessorFigure 7.26 Write Cycle, Slow Memory (≥ 64 Kbyte)MAD(Driven by LSI53C875)MAS2/(Driven by LSI53C875)MAS1/(Driv

PCI and External Memory Interface Timing Diagrams 7-43Figure 7.26 Write Cycle, Slow Memory (≥ 64 Kbyte) (Cont.)MAD(Driven by LSI53C875)MAS2/(Driven by

2-4 Functional DescriptionSDMS software includes a SCSI BIOS to manage all SCSI functionsrelated to the device. It also provides a series of SCSI devi

7-44 Instruction Set of the I/O ProcessorFigure 7.27 Read Cycle, Normal/Fast Memory (≥ 64 Kbyte)t19t17MADHigh Ordert11Data driven by memory)MAS2/(Driv

PCI and External Memory Interface Timing Diagrams 7-45Figure 7.28 Write Cycle, Normal/Fast Memory (≥ 64 Kbyte)MADHigh OrderMAS2/(Driven by LSI53C875)M

7-46 Instruction Set of the I/O ProcessorFigure 7.29 Read Cycle, Slow Memory (≤ 64 Kbyte)MAD(Address driven by LSI53C875Data driven by memory)MAS2/(Dr

PCI and External Memory Interface Timing Diagrams 7-47Figure 7.29 Read Cycle, Slow Memory (≤ 64 Kbyte) (Cont.)MAD(Address driven by LSI53C875Data driv

7-48 Instruction Set of the I/O ProcessorFigure 7.30 Write Cycle, Slow Memory (≤ 64 Kbyte)MADMAS2/(Driven by LSI53C875)MAS1/(Driven by LSI53C875)MAS0/

PCI and External Memory Interface Timing Diagrams 7-49Figure 7.30 Write Cycle, Slow Memory (≤ 64 Kbyte) (Cont.)MADMAS2/(Driven by LSI53C875)MAS1/(Driv

7-50 Instruction Set of the I/O Processor7.5 PCI and External Memory Interface TimingTable 7.19 lists the LSI53C875 PCI and External Memory Interface

SCSI Timing Diagrams 7-517.6 SCSI Timing DiagramsTable 7.20 through Table 7.29 and Figure 7.31 through Figure 7.35describe the LSI53C875 SCSI timing.F

7-52 Instruction Set of the I/O ProcessorFigure 7.32 Initiator Asynchronous ReceiveFigure 7.33 Target Asynchronous SendTable 7.21 Initiator Asynchrono

SCSI Timing Diagrams 7-53Figure 7.34 Target Asynchronous ReceiveFigure 7.35 Initiator and Target Synchronous TransferTable 7.23 Target Asynchronous Re

Prefetching SCRIPTS Instructions 2-5Step 1. Set the SCLK Doubler Enable bit (SCSI Test One (STEST1),bit 3).Step 2. Wait 20 µs.Step 3. Halt the SCSI cl

7-54 Instruction Set of the I/O ProcessorTable 7.24 SCSI-1 Transfers (SE, 5.0 Mbytes/s)Symbol Parameter Min Max Unitt1Send SREQ/ or SACK/ assertion pu

SCSI Timing Diagrams 7-55Table 7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s(16-Bit Transfers), 40 MHz ClockSymbol Param

7-56 Instruction Set of the I/O ProcessorTable 7.28 Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers) or 40.0 Mbytes/s(16-Bit Transfers), 80 MHz

SCSI Timing Diagrams 7-57Table 7.29 Ultra SCSI Differential Transfers 20.0 Mbytes/s (8-Bit Transfers) or40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock

7-58 Instruction Set of the I/O Processor7.7 Package DrawingsFigure 7.36 is the 169-pin PBGA mechanical drawing and Figure 7.37 isthe 160-pin PQFP mec

Package Drawings 7-59Figure 7.37 160-pin PQFP (P3) Mechanical Drawing (Sheet 1 of 2)Important: This drawing may not be the latest version. For board l

7-60 Instruction Set of the I/O ProcessorFigure 7.37 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2)Important: This drawing may not be the latest

LSI53C875/875E PCI to Ultra SCSI I/O Processor A-1Appendix ARegister SummaryTable A.1 lists the LSI53C875 configuration registers by register name.Tabl

A-2 Register SummaryTable A.2 lists the LSI53C875 operating registers by register name.Power Management Capabilities 0x42 Read Only 3-25Power Manageme

Register Summary A-3DMA Interrupt Enable (DIEN) 0x39 (0xB9) Read/Write 5-50DMA Mode (DMODE) 0x38 (0xB8) Read/Write 5-47DMA Next Address (DNAD) 0x28–0x

Preface iiiPrefaceThis book is the primary reference and technical manual for the LSI LogicLSI53C875/875E PCI to Ultra SCSI I/O Processor. It contains

2-6 Functional Description• On every Store instruction. The Store instruction may also be usedto place modified code directly into memory. To avoid ina

A-4 Register SummarySCSI Destination ID (SDID) 0x06 (0x86) Read/Write 5-18SCSI First Byte Received (SFBR) 0x08 (0x88) Read/Write 5-20SCSI Input Data L

LSI53C875/875E PCI to Ultra SCSI I/O Processor B-1Appendix BExternal MemoryInterface DiagramExamplesFigure B.1 64 Kbyte Interface with 200 ns MemoryLS

B-2 External Memory Interface Diagram ExamplesFigure B.2 64 Kbyte Interface with 150 ns MemoryLSI53C87527C512-15/MOE/OEMCE/CE8MAD[7:0]Bus8A[7:0]8A[15:

External Memory Interface Diagram Examples B-3Figure B.3 256 Kbyte Interface with 150 ns MemoryLSI53C87527C020-15/MOE/OEMCE/CE8MAD[7:0]Bus8A[7:0]8A[15

B-4 External Memory Interface Diagram ExamplesFigure B.4 512 Kbyte Interface with 150 ns MemoryLSI53C875MOE/8MAD[7:0]Bus8A[7:0]8A[15:8]8VSSMAS0/MAS1/8

LSI53C875/875E PCI to Ultra SCSI I/O Processor IX-1IndexNumerics3.3/5 volt PCI interface 2-93-state 4-6Aabort operation bit 5-31aborted bit 5-24, 5-50

IX-2 IndexDIF bit 5-73differential modeDIFFSENS 4-19direction control pins 4-16operation 2-20SCSI differential mode bit 5-73DIFFSENS SCSI signal 7-3di

Index IX-3MMACNTL register 5-62MAD bus programming 4-22MAD[0] 4-24MAD[3:1] 4-24MAD[4] 4-23MAD[5] 4-23MAD[6] 4-23MAD[7] 4-22manual start mode bit 5-49m

IX-4 Indexsubsystem vendor ID (SSVID) 3-20vendor ID 3-13PCI configuration space 3-1PCI I/O space 3-2PCI memory space 3-2PCI timings 7-50phase mismatch

Index IX-5byte offset counter 5-39, 5-43cache line size enable 5-51chained mode 5-9chip revision level 5-37chip type 5-62clear DMA FIFO 5-37clear SCSI

External Memory Interface 2-7updates are required, a 7406 (high voltage open collector inverter), anMTD4P05, and several passive components are also n

IX-6 IndexSODR most significant byte full 5-29software reset 5-32source I/O memory enable 5-48SREQ/ status 5-22SSEL/ status 5-22start DMA operation 5-

Index IX-7select with SATN/ on a start sequence bit 5-4selected bit 5-54, 5-57selection or reselection time-out bit 5-56, 5-59selection response logic

IX-8 Index

LSI53C875/875E PCI to Ultra SCSI I/O ProcessorCustomer FeedbackWe would appreciate your feedback on this document. Please copy thefollowing page, add

Customer FeedbackReader’s CommentsFax your comments to: LSI Logic CorporationTechnical PublicationsM/S E-198Fax: 408.433.4333Please tell us how you ra

2-8 Functional Descriptionnecessary since there are internal pull-ups on the MAD bus. The internalpull-up resistors are disabled when external pull-do

PCI Cache Mode 2-92.5.2 3.3 V/5 V PCI InterfaceThe LSI53C875 can attach directly to a 3.3 V ora5VPCIinterface, dueto separate VDDpins for the PCI bus

2-10 Functional Description2.5.4 JTAG Boundary Scan TestingThe LSI53C875J/LSI53C875N/LSI53C875JB include support for JTAGboundary scan testing in acco

PCI Cache Mode 2-11location 0x0000 from memory is routed to lane three, and the data atlocation 0x0003 is routed to byte lane 0. In little endian mode

2-12 Functional DescriptionSoftware drivers for the LSI53C875 should access registers by theirlogical name (that is, SCNTL0) rather than by their addr

PCI Cache Mode 2-13slave write operations causes a fatal DMA interrupt; SCRIPTS stopsrunning. Mask this interrupt with the EBPE Interrupt Enable bit,

2-14 Functional DescriptionMaster Data Parity Error DMA Status(DSTAT), Bit 6Set when the LSI53C875 as a master detects that atarget device has signale

PCI Cache Mode 2-152.5.8 DMA FIFOThe DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFOis illustrated in Figure 2.1. To assure compatibility

iv Preface• Chapter 6, Instruction Set of the I/O Processor, defines all of theSCSI SCRIPTS instructions that are supported by the LSI53C875.• Chapter

2-16 Functional Description2.5.8.1 Data PathsThe data path through the LSI53C875 is dependent on whether data isbeing moved into or out of the chip, a

PCI Cache Mode 2-17The following steps determine if any bytes remain in the data path whenthe chip halts an operation:Asynchronous SCSI Send –Step 1.

2-18 Functional Descriptionthe DMA FIFO Byte Offset Counter, which consists of bits [1:0]in the CTEST5 register and bits [7:0] of the DMA FIFO registe

PCI Cache Mode 2-19Step 3. If any wide transfers have been performed using the ChainedMove instruction, read the Wide SCSI Receive bit (SCSIControl Tw

2-20 Functional Description2.5.9.1 Differential ModeIn differential mode, the SDIR[15:0], SDIRP[1:0], IGS, TGS, RSTDIR,BSYDIR, and SELDIR signals cont

PCI Cache Mode 2-21To interface the LSI53C875 to the SN75976A, connect the DIR pins, aswell as IGS and TGS, of the LSI53C875 directly to the transceiv

2-22 Functional DescriptionFigure 2.3 Differential Wiring DiagramLSI53C8XXSELDIRBSYDIRRSTDIRSEL/BSY/RST/REQ/ACK/MSG/C/D/I/O/ATN/TGSIGSSD[8:15]/SDP1/SD

PCI Cache Mode 2-232.5.9.2 Terminator NetworksThe terminator networks provide the biasing needed to pull signals to aninactive voltage level, and to m

2-24 Functional DescriptionFigure 2.4 Regulated TerminationTERML1TERML2TERML3TERML4TERML5TERML6TERML7TERML8TERML9TERML10TERML11TERML12TERML13TERML14TE

PCI Cache Mode 2-252.5.10 Select/Reselect During Selection/ReselectionIn multithreaded SCSI I/O environments, it is not uncommon to beselected or rese

Preface vLSI Logic World Wide Web Home Pagewww.lsilogic.comSCSI SCRIPTS™ Processors Programming Guide, Version 2.2,Order Number S14044.APCI Special In

2-26 Functional Description2.5.11.1 Determining the Data Transfer RateSynchronous data transfer rates are controlled by bits in two differentregisters

PCI Cache Mode 2-27example, if SCLK is 80 MHz and the SCF value is set to divide by two,then the maximum rate at which data can be received is 10 MHz(

2-28 Functional Descriptiona value of 101 (binary), allowing the SCLK frequency to be divideddown by 4. This allows systems using an 80 MHz clock or t

PCI Cache Mode 2-29a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be thefirst interrupt serviced. It must be written to one to be cle

2-30 Functional DescriptionIf the DFE bit is cleared, then the FIFOs must be cleared by setting theCLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits

PCI Cache Mode 2-31behavior when the SATN/ interrupt is enabled during Target modeoperation. The Interrupt-on-the-Fly interrupt is also nonfatal, sinc

2-32 Functional DescriptionIf you are polling the ISTAT instead of using hardware interrupts, thenmasking a fatal interrupt makes no difference since

PCI Cache Mode 2-33As previously mentioned, DMA interrupts do not attempt to flush theFIFOs before generating the interrupt. It is important to set eit

2-34 Functional Description1. Read Interrupt Status (ISTAT).2. If the INTF bit is set, it must be written to a one to clear this status.3. If only the

PCI Cache Mode 2-35Figure 2.6 Block Move and Chained Block Move InstructionsCHMOV 5, 3 when Data_OutMoves five bytes from address 0x03 in the host memo

vi Preface

2-36 Functional Descriptionsend transfer. When the WSS flag is set at the start of the next transfer,the first byte (the high-order byte) of the next da

PCI Cache Mode 2-372.5.14.5 Chained Block Move SCRIPTS InstructionA chained Block Move SCRIPTS instruction is primarily used to transferconsecutive da

2-38 Functional DescriptionBlock Move instruction is used, if the WSS bit is set at the start of a datasend command, the first byte of the data send co

Power Management 2-392.6.2 Power State D3Power state D3 is the minimum power state, which includes subsettingscalled D3hot and D3cold. The devices are

2-40 Functional Description

LSI53C875/875E PCI to Ultra SCSI I/O Processor 3-1Chapter 3PCI FunctionalDescriptionThis chapter is divided into the following sections:• Section 3.1,

3-2 PCI Functional Descriptionaddress assigned through the configured register. The LSI53C875operating registers are available in both the upper and lo

PCI Addressing 3-33.1.1.1 I/O Read CommandThe I/O Read command reads data from an agent mapped in I/Oaddress space. All 32 address bits are decoded.3.

3-4 PCI Functional Description3.1.1.3 Memory ReadThe Memory Read command reads data from an agent mapped inmemory address space. All 32 address bits a

PCI Cache Mode 3-53.2.2 Selection of Cache Line SizeThe cache logic selects a cache line size based on the values for theburst size in the DMA Mode (D

Contents viiContentsChapter 1 General Description1.1 Package and Feature Options 1-41.2 Benefits of Ultra SCSI 1-41.3 TolerANT®Technology 1-51.4 LSI53C

3-6 PCI Functional DescriptionExample: Cache Line Size - 16, Current Address = 0x01 – The chipis not aligned to a 4 Dword cache boundary (the stepping

PCI Cache Mode 3-72. The Cache Line Size register contains a legal burst size (2, 4, 8, 16,32, 64, or 128) value and that value must be less than or e

3-8 PCI Functional Descriptiontransfer at a later time using another bus ownership. If the chip istransferring multiple cache lines it continues to tr

PCI Cache Mode 3-91. The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL)register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE)register)

3-10 PCI Functional DescriptionBurst Size Selection – The Read Multiple command reads in multiplecache lines of data in a single bus ownership. The nu

Configuration Registers 3-113.3 Configuration RegistersThe Configuration registers are accessible only by the system BIOSduring PCI configuration cycles.

3-12 PCI Functional DescriptionTable 3.2 PCI Configuration Register Map31 16 15 0Device ID Vendor ID 0x00Status Command 0x04Class Code Revision ID 0x08

Configuration Registers 3-13Register: 0x00Vendor IDRead OnlyVID Vendor ID [15:0]This 16-bit register identifies the manufacturer of thedevice. The Vendo

3-14 PCI Functional DescriptionR Reserved [15:9]SERR/ Enable 8This bit enables the SERR/ driver. SERR/ is disabledwhen this bit is cleared. The defaul

Configuration Registers 3-15EIS Enable I/O Space 0This bit controls the LSI53C875 response to I/O spaceaccesses. A value of zero disables the device re

viii Contents2.5.4 JTAG Boundary Scan Testing 2-102.5.5 Big and Little Endian Support 2-102.5.6 Loopback Mode 2-122.5.7 Parity Options 2-122.5.8 DMA F

3-16 PCI Functional DescriptionR Reserved 11DT[1:0] DEVSEL/Timing [10:9]These bits encode the timing of DEVSEL/. These areencoded asThese bits are rea

Configuration Registers 3-17Register: 0x08Revision IDRead OnlyRID Revision ID [7:0]This register specifies device and revision identifiers. Thevalue of t

3-18 PCI Functional DescriptionRegister: 0x0CCache Line SizeRead/WriteCLS Cache Line Size [7:0]This register specifies the system cache line size in un

Configuration Registers 3-19Register: 0x0EHeader TypeRead OnlyHT Header Type [7:0]This register identifies the layout of bytes 0x10 through0x3F in config

3-20 PCI Functional DescriptionRegister: 0x18RAM Base Address Two (Memory) SCRIPTS RAMRead/WriteBAR2 Base Address Register Two [31:0]This register hol

Configuration Registers 3-21Register: 0x2ESubsystem ID (SSID)Read OnlySSID Subsystem ID [15:0]This register supports subsystem identification, which has

3-22 PCI Functional DescriptionThe Expansion ROM Enable bit, bit 0, is the only bitdefined in this register. This bit is used to control whetheror not

Configuration Registers 3-23Register: 0x3CInterrupt LineRead/WriteIL Interrupt Line [7:0]This register is used to communicate interrupt line routinginf

3-24 PCI Functional DescriptionRegister: 0x3EMin_GntRead OnlyMG Min_Gnt [7:0]This register is used to specify the desired settings forlatency timer va

Configuration Registers 3-25Register: 0x40Capability IDRead OnlyCID Cap_ID [7:0]This register indicates the type of data structure currentlybeing used.

Contents ix6.2 Block Move Instructions 6-56.2.1 First Dword 6-56.2.2 Second Dword 6-126.3 I/O Instruction 6-126.3.1 First Dword 6-126.3.2 Second Dword

3-26 PCI Functional DescriptionPMES PME Support [15:11]This field is always set to 00000b because theLSI53C875E does not provide a PME signal.D2S D2 Su

Configuration Registers 3-27PST PME Status 15The device always returns a zero for this bit, indicatingthat PME signal generation is not supported from

3-28 PCI Functional DescriptionRegister: 0x47DataRead OnlyDATA Data [7:0]This register applies to the LSI53C875E only andprovides an optional mechanis

LSI53C875/875E PCI to Ultra SCSI I/O Processor 4-1Chapter 4Signal DescriptionsThis chapter presents the LSI53C875 pin configuration and signaldefinition

4-2 Signal DescriptionsFigure 4.1 LSI53C875 Pin DiagramC_BE3/AD23AD22VDD-IAD18C_BE2/IRDY/VSSSTOP/PAR/VSSAD15AD11VSSAD8C_BE0/13579111315171921232527293

4-3Figure 4.2 LSI53C875J Pin DiagramC_BE3/AD23AD22VDD-IAD18C_BE2/IRDY/VSSSTOP/PAR/VSSAD15AD11VSSAD8C_BE0/13579111315171921232527293133353637383940AD17

4-4 Signal DescriptionsFigure 4.3 LSI53C875N Pin DiagramNCNCNCBYTEPAR2AD22AD19AD18AD17FRAME/TRDY/VDD-ISTOP/BYTEPAR1AD13VSSAD12135791113151719212325272

4-5Figure 4.4 LSI53C875JB Pin Diagram (Top View)Note: Pins F7, G6, G7, G8, and H7 are connected to the die pad.A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

4-6 Signal DescriptionsThe PCI/SCSI pin definitions are organized into the following functionalgroups: System, Address/Data, Interface Control, Arbitra

4-7Table 4.1 describes the LSI53C875, LSI53C875J, LSI53C875E, andLSI53C875JE Power and Ground Signals group.Table 4.2 describes the LSI53C875N Power a