Avago-technologies PEX 8605 Manuel d'utilisateur télécharger pdf

PEX8605

1 Introduction

This document is intended for systems design engineers incorporating the PEX8605 PCI Express switch into a

system hardware design. It provides a handy list of basic design checks covering schematic and printed-circuit

board (PCB) layout designs. Including these checks as part of your design review can help insure that

important details are not overlooked when your design is committed to hardware, thereby improving your

chances for a successful bring-up. In preparation for your design review, we also recommend that you check

our website, www.plxtech.com, and download the most current technical specifications, errata, and related

documentation. This document supersedes and replaces previously dated versions.

2 Schematic Design Checks

This section includes checks on basic elements of the circuit design, including schematic symbol, power

supply, configuration straps, clocks, reset, configuration serial EEPROM, I2C, JTAG, GPIO, and other signals.

All power and signal pins on the device are covered.

2.1 Schematic Symbol

For designers using ORCAD schematic capture tools, an ORCAD symbol library is available on the PLX

website at www.plxtech.com. This library symbol is pre-checked by PLX engineers.

For designers not using the PLX-supplied schematic symbol, we highly recommend double-checking your

symbol’s signal pin names and numbers for accuracy before using the symbol in your schematic design.

2.2 Power Supply

2.2.1 Regulated DC Supply Voltages

The PEX8605 requires the following regulated DC voltages:

 Core Logic Supply: 1.0 Volts (0.95V – 1.10V) – Powers core logic, SerDes Digital, and PLL

 IO Supply: 2.5 or 3.3 Volts (2.3V – 3.6V) - Powers external I/O, SerDes Analog

2.2.2 Power Supply Sequencing Requirements

The Core Logic and IO supplies can be sequenced in any order. No special hardware is required to control the

order in which the power supply rails power up and down. It is recommended that both supplies be powered

up or down together.

1 2 3 4 5 6 ... 12 13

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Page 1 - 2 Schematic Design Checks

PEX8605 © PLX Technology, www.plxtech.com Page 1 of 13 2 May 2013, version 1.7 1 Introduction This document is intended for systems design enginee

Page 2

PEX8605 © PLX Technology, www.plxtech.com Page 10 of 13 2 May 2013, version 1.7 Signal Name Dual-Row QFN Pkg. Pin # TQFP Package Pin # Signal Type

Page 3

PEX8605 © PLX Technology, www.plxtech.com Page 11 of 13 2 May 2013, version 1.7 Signal Name Dual-Row QFN Pkg. Pin # TQFP Package Pin # Signal Type

Page 4

PEX8605 © PLX Technology, www.plxtech.com Page 12 of 13 2 May 2013, version 1.7 2.14 Additional Schematic Design Considerations 2.14.1 Mid-Bus Pro

Page 5

PEX8605 © PLX Technology, www.plxtech.com Page 13 of 13 2 May 2013, version 1.7 8. Match left/right turn bends where possible. No 90-degree bends

Page 6

PEX8605 © PLX Technology, www.plxtech.com Page 2 of 13 2 May 2013, version 1.7 2.3 Power, Ground Pin Connections Signal Name Dual-Row QFN Pkg. Pin

Page 7

PEX8605 © PLX Technology, www.plxtech.com Page 3 of 13 2 May 2013, version 1.7 Signal Name Dual-Row QFN Pkg. Pin # TQFP Package Pin # Signal Type C

Page 8

PEX8605 © PLX Technology, www.plxtech.com Page 4 of 13 2 May 2013, version 1.7 2.4 Clocks 2.4.1 Clock Source and Line Termination REFCLK Source S

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PEX8605 © PLX Technology, www.plxtech.com Page 5 of 13 2 May 2013, version 1.7 Signal Name Dual-Row QFN Pkg. Pin # TQFP Package Pin # Signal Type C

Page 10

PEX8605 © PLX Technology, www.plxtech.com Page 6 of 13 2 May 2013, version 1.7 Signal Name Dual-Row QFN Pkg. Pin # TQFP Package Pin # Signal Type C

Page 11

PEX8605 © PLX Technology, www.plxtech.com Page 7 of 13 2 May 2013, version 1.7 2.8 Serial EEPROM As of this writing, a serial configuration EEPROM

Page 12 - 3 PCB Layout Design Checks

PEX8605 © PLX Technology, www.plxtech.com Page 8 of 13 2 May 2013, version 1.7 2.9 JTAG Interface – 5 Pins Signal Name Dual-Row QFN Pkg. Pin # TQF

Page 13

PEX8605 © PLX Technology, www.plxtech.com Page 9 of 13 2 May 2013, version 1.7 2.11 Device-Specific Signals Signal Name Dual-Row QFN Pkg. Pin # T

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Avago-technologies PEX 8605 Manuel d'utilisateur

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