Avago-technologies LSI53C895A Manuel d'utilisateur

®S14028.BLSI53C895APCI to Ultra2SCSI ControllerTECHNICALMANUALApril 2001Version 2.2

xContentsChapter 6 Electrical Specifications6.1 DC Characteristics 6-16.2 TolerANT Technology Electrical Characteristics 6-86.3 AC Characteristics 6-1

3-12 Signal Descriptions3.4.2 SCSI SignalsTable 3.10 describes the SCSI signals.Table 3.10 SCSI SignalsName PQFP BGA Pos Type Strength DescriptionSD[1

SCSI Bus Interface Signals 3-133.4.3 SCSI Control SignalsTable 3.11 describes the SCSI Control signals.Table 3.11 SCSI Control SignalsName PQFP BGA Po

3-14 Signal Descriptions3.5 Flash ROM and Memory Interface SignalsTable 3.12 describes the Flash ROM and Memory Interface signals.Table 3.12 Flash ROM

Flash ROM and Memory Interface Signals 3-15MAS1/ 185 M1 O 4 mA Memory Address Strobe 1. Thispinisusedtolatchinthemostsignificant address byte (bits [1

3-16 Signal Descriptions3.6 Test Interface SignalsTable 3.13 describes Test Interface signals.Table 3.13 Test Interface SignalsName PQFP BGA Pos Type

Power and Ground Signals 3-173.7 Power and Ground SignalsTable 3.14 describes the Power and Ground signals.Table 3.14 Power and Ground SignalsName PQF

3-18 Signal DescriptionsNC 4, 49, 53, 62,103–109,152–159, 177,192, 207, 208A2, A6,A19–A20, B1,B11, B17–18,C2–9,C11–16, C18,D5, D7,D9–10, D12,D14, E2–4

MAD Bus Programming 3-193.8 MAD Bus ProgrammingThe MAD[7:0] pins, in addition to serving as the address/data bus for thelocal memory interface, also a

3-20 Signal Descriptions• MAD[3:1] – These pins are used to set the size of the externalexpansion ROM device attached. Encoding for these pins are lis

LSI53C895A PCI to Ultra2 SCSI Controller 4-1Chapter 4RegistersThis chapter describes all LSI53C895A registers and is divided into thefollowing section

Contents xi6.3 Rise and Fall Time Test Condition 6-96.4 SCSI Input Filtering 6-96.5 Hysteresis of SCSI Receivers 6-106.6 Input Current as a Function o

4-2 Registersnot supported are not writable and return all zeros when read. Only thoseregisters and bits that are currently supported by the LSI53C895

PCI Configuration Registers 4-3Registers:0x00–0x01Vendor IDRead OnlyVID Vendor ID [15:0]This 16-bit register identifies the manufacturer of thedevice.

4-4 RegistersR Reserved [15:9]SE SERR/ Enable 8This bit enables the SERR/ driver. SERR/ is disabledwhen this bit is cleared. The default value of this

PCI Configuration Registers 4-5EIS Enable I/O Space 0This bit controls the LSI53C895A response to I/O spaceaccesses. A value of zero disables the devi

4-6 RegistersR Reserved 11DT[1:0] DEVSEL/ Timing [10:9]These bits encode the timing of DEVSEL/. These areencoded as:These bits are read only and shoul

PCI Configuration Registers 4-7Register: 0x08Revision ID (Rev ID)Read OnlyRID Revision ID [7:0]This register contains the current revision level of th

4-8 Registerswhether to use Read, Read Line, or Read Multiplecommands for performing read cycles as a bus master.Devices participating in the caching

PCI Configuration Registers 4-9Register: 0x0FNot SupportedRegisters:0x10–0x13Base Address Register Zero (I/O)Read/WriteBAR0 Base Address Register Zero

4-10 RegistersRegisters:0x18–0x1BBase Address Register Two (SCRIPTS RAM)Read/WriteBAR2 Base Address Register Two [31:0]This base register is used to m

PCI Configuration Registers 4-11vendor’s cards, even if the cards have the same PCIcontroller installed on them (and therefore the sameVendor ID and D

xii Contents6.37 Target Asynchronous Send 6-586.38 Target Asynchronous Receive 6-596.39 Initiator and Target Synchronous Transfer 6-636.40 LSI53C895A

4-12 RegistersIf the external serial EEPROM interface is enabled(MAD[7] is LOW), this register is automatically loaded atpower-up from the external se

PCI Configuration Registers 4-13The host system detects the size of the external memoryby first writing the Expansion ROM Base Address registerwith al

4-14 Registerscontroller(s) the device’s interrupt pin is connected to.Values in this register are specified by systemarchitecture.Register: 0x3DInter

PCI Configuration Registers 4-15Register: 0x3FMax_LatRead OnlyML MAX_LAT [7:0]This register is used to specify the desired settings forlatency timer v

4-16 RegistersRegisters:0x42–0x43Power Management Capabilities (PMC)Read OnlyPMES PME_Support [15:11]Bits [15:11] define the power management states i

PCI Configuration Registers 4-17Registers:0x44–0x45Power Management Control/Status (PMCSR)Read/WritePST PME Status 15The LSI53C895A always returns a z

4-18 RegistersRegister: 0x46Bridge Support Extensions (PMCSR_BSE)Read OnlyBSE Bridge Support Extensions [7:0]This register indicates PCI Bridge specif

SCSI Registers 4-19additional information about using this register refer to theSection 2.5, “Alternative SSVID/SSID LoadingMechanism,” topic in Chapt

4-20 RegistersTable 4.2 SCSI Register Address Map31 16 15 0SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00GPREG0 SDID SXFER SCID 0x04SBCL SSID SOCL SFBR 0x08SSTAT2 S

SCSI Registers 4-21Register: 0x00SCSI Control Zero (SCNTL0)Read/WriteARB[1:0] Arbitration Mode Bits 1 and 0 [7:6]Simple Arbitration1. The LSI53C895A w

Contents xiii3.14 Power and Ground Signals 3-173.15 Decode of MAD Pins 3-204.1 PCI Configuration Register Map 4-24.2 SCSI Register Address Map 4-204.3

4-22 RegistersFull Arbitration, Selection/Reselection1. The LSI53C895A waits for a bus free condition.2. It asserts SBSY/ and its SCSI ID (the highest

SCSI Registers 4-23WATN Select with SATN/ on a Start Sequence 4When this bit is set and the LSI53C895A is in the initiatormode, the SATN/ signal is as

4-24 Registers(SET TARGET or CLEAR TARGET). When this bit is set, thechip is a target device by default. When this bit is cleared,the LSI53C895A is an

SCSI Registers 4-25may transfer up to three additional bytes before halting tosynchronize between internal core cells. Duringsynchronous operation, th

4-26 Registersfor multithreaded applications. The ARB[1:0] bits in theSCSI Control Zero (SCNTL0) register are set for fullarbitration and selection be

SCSI Registers 4-27Caution: Writing to this register while not connected may cause theloss of a selection/reselection by clearing the Connectedbit.Reg

4-28 Registers(SODL) register during a send operation. This byte iscombined with the first byte from the subsequent transferso that a wide transfer is

SCSI Registers 4-29count if the first byte received is one of the standardgroup codes. If this bit is set, the device does not reloadthe Block Move by

4-30 RegistersNote: Set this bit to achieve Ultra SCSI transfer rates in legacysystems that use an 80 MHz clock.SCF[2:0] Synchronous Clock Conversion

SCSI Registers 4-31Note: It is important that these bits are set to the proper valuesto guarantee that the LSI53C895A meets the SCSI timingsas defined

xiv Contents6.15 External Clock 6-126.16 Reset Input 6-136.17 Interrupt Output 6-146.18 PCI Configuration Register Read 6-166.19 PCI Configuration Reg

4-32 RegistersRegister: 0x05SCSI Transfer (SXFER)Read/WriteNote:When using Table Indirect I/O commands, bits [7:0] of thisregister are loaded from the

SCSI Registers 4-33(This SCSI synchronous core clock is determined inSCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is assertedand the LSI53C895A is sen

4-34 RegistersTable 4.4 shows example transfer periods and rates for fast SCSI-2 andUltra SCSI.MO[4:0] Max SCSI Synchronous Offset [4:0]These bits des

SCSI Registers 4-35Table 4.5 Maximum Synchronous OffsetMO4 MO3 MO2 MO1 MO0 Synchronous Offset00000 0-Asynchronous00001 100010 200011 300100 400101 500

4-36 RegistersRegister: 0x06SCSI Destination ID (SDID)Read/WriteR Reserved [7:4]ENC Encoded Destination SCSI ID [3:0]Writing these bits set the SCSI I

SCSI Registers 4-37is also possible to program these signals as live inputsand sense them through a SCRIPTS register to registerMove Instruction. GPIO

4-38 RegistersThis register also contains the state of the lower eight bits of the SCSIdata bus during the Selection phase if the COM bit in the DMA C

SCSI Registers 4-39Register: 0x0ASCSI Selector ID (SSID)Read OnlyVAL SCSI Valid 7If VAL is asserted, then the two SCSI IDs are detectedon the bus duri

4-40 RegistersREQ SREQ/ Status 7ACK SACK/ Status 6BSY SBSY/ Status 5SEL SSEL/ Status 4ATN SATN/ Status 3MSG SMSG/ Status 2C_D SC_D/ Status 1I_O SI_O/

SCSI Registers 4-41MDPE Master Data Parity Error 6This bit is set when the LSI53C895A as a master detectsa data parity error, or a target device signa

Contents xv6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-616.49 Ultra SCSI Hig

4-42 Registers• During a Transfer Control instruction, the CompareData (bit 18) and Compare Phase (bit 17) bits are setin the DMA Byte Counter (DBC) r

SCSI Registers 4-43Register: 0x0DSCSI Status Zero (SSTAT0)Read OnlyILF SIDL Least Significant Byte Full 7This bit is set when the least significant by

4-44 RegistersAIP Arbitration in Progress 4Arbitration in Progress (AIP = 1) indicates that theLSI53C895A has detected a Bus Free condition, assertedS

SCSI Registers 4-45SCSIFIFOcanholdupto31bytesfornarrowSCSIsynchronous data transfers, or up to 31 words for wide.Values over 31 will not occur.Table 4

4-46 RegistersSDP0L Latched SCSI Parity 3This bit reflects the SCSI parity signal (SDP0/),corresponding to the data latched in the SCSI Input DataLatc

SCSI Registers 4-47OLF1 SODL Most Significant Byte Full 5This bit is set when the most significant byte in the SCSIOutput Data Latch (SODL) contains d

4-48 RegistersSDP1 SCSI SDP1 Signal 0This bit represents the active HIGH current state of theSCSI SDP1 parity signal. It is unlatched and may changeas

SCSI Registers 4-491. Set this bit.2. Wait for an interrupt.3. Read the Interrupt Status Zero (ISTAT0) andInterrupt Status One (ISTAT1) registers.4. I

4-50 RegistersSEM Semaphore 4The SCRIPTS processor may set this bit using aSCRIPTS register write instruction. An external processormay also set it wh

SCSI Registers 4-51• A phase mismatch (initiator mode) or SATN/ becomesactive (target mode)• An arbitration sequence completes• A selection or reselec

xvi Contents

4-52 RegistersRegister: 0x15Interrupt Status One (ISTAT1)Read/WriteR Reserved [7:3]FLSH Flushing 2Reading this bit monitors if the chip is currently f

SCSI Registers 4-53Register: 0x16Mailbox Zero (MBOX0)Read/WriteMBOX0 Mailbox Zero [7:0]These are general purpose bits that may be read orwritten while

4-54 RegistersRegister: 0x18Chip Test Zero (CTEST0)Read/WriteFMT Byte Empty in DMA FIFO [7:0]These bits identify the bottom bytes in the DMA FIFO that

SCSI Registers 4-55Register: 0x1AChip Test Two (CTEST2)Read Only (bit 3 write)DDIR Data Transfer Direction 7This status bit indicates which direction

4-56 RegistersWhen it is set, the SCRATCHA register contains bits[31:0] of the Memory Base Address value from the PCIBase Address Register One (MEMORY

SCSI Registers 4-57Register: 0x1BChip Test Three (CTEST3)Read/WriteV ChipRevisionLevel [7:4]These bits identify the chip revision level for softwarepu

4-58 RegistersWRIE Write and Invalidate Enable 0This bit, when set, causes the issuing of Write andInvalidate commands on the PCI bus whenever legal.

SCSI Registers 4-59Once the chip has stopped transferring data, these bitsare stable.The DMA FIFO (DFIFO) register counts the number ofbytes transferr

4-60 RegistersRegister: 0x21Chip Test Four (CTEST4)Read/WriteBDIS Burst Disable 7When set, this bit causes the LSI53C895A to performback-to-back cycle

SCSI Registers 4-61LSI53C895A is informed of the error by the PERR/ pinbeing asserted by the target. When this bit is cleared, theLSI53C895A does not

LSI53C895A PCI to Ultra2 SCSI Controller 1-1Chapter 1General DescriptionChapter 1 is divided into the following sections:• Section 1.1, “New Features

4-62 RegistersRegister: 0x22Chip Test Five (CTEST5)Read/WriteADCK Clock Address Incrementor 7Setting this bit increments the address pointer contained

SCSI Registers 4-63transferred from the SCSI bus to the host bus.Deasserting the internal DMA write signal transfers datafrom the host bus to the SCSI

4-64 RegistersRegisters:0x24–0x26DMA Byte Counter (DBC)Read/WriteDBC DMA Byte Counter [23:0]This 24-bit register determines the number of bytestransfe

SCSI Registers 4-65Register: 0x27DMA Command (DCMD)Read/WriteDCMD DMA Command [7:0]This 8-bit register determines the instruction for theLSI53C895A to

4-66 Registersthe SCRIPT is written to this register, SCRIPTS areautomatically fetched and executed until an interruptcondition occurs.In single step

SCSI Registers 4-67Registers:0x34–0x37Scratch Register A (SCRATCHA)Read/WriteSCRATCHA Scratch Register A [31:0]This is a general purpose, user-definab

4-68 Registersend-of-transfer cleanup and alignment, even if less thana full burst of transfers is performed. The LSI53C895Ainserts a “fairness delay”

SCSI Registers 4-69DIOM Destination I/O Memory Enable 4This bit is defined as an I/O Memory Enable bit for thedestination address of a Memory Move or

4-70 Registersautomatically begin fetching and executing SCSISCRIPTS when the DSP register is written. This bitnormally is not used for SCSI SCRIPTS o

SCSI Registers 4-71The IRQ/ output is latched. Once asserted, it will remain asserted untilthe interrupt is cleared by reading the appropriate status

1-2 General Descriptionstandards. It implements multithreaded I/O algorithms with a minimum ofprocessor intervention, solving the protocol overhead pr

4-72 RegistersPFEN Prefetch Enable 5Setting this bit enables an 8-Dword SCRIPTS instructionprefetch unit. The prefetch unit, when enabled, will fetch8

SCSI Registers 4-73IRQM IRQ Mode 3When set, this bit enables a totem pole driver for the IRQ/pin. When cleared, this bit enables an open drain driverf

4-74 RegistersWhen the COM bit is set, the ID is stored only in theSSID register, protecting the SFBR from beingoverwritten if a selection/reselection

SCSI Registers 4-75Disable Halt on Parity Error or SATN/ Condition bit in theSCSI Control One (SCNTL1) register for moreinformation on when this statu

4-76 RegistersControl Two (SCNTL2) register for more information onexpected versus unexpected disconnects. Any disconnectin low level mode causes this

SCSI Registers 4-77R Reserved 3STO Selection or Reselection Time-out 2The SCSI device which the LSI53C895A is attempting toselect or reselect does not

4-78 RegistersWhen performing consecutive 8-bit reads of the DMA Status (DSTAT),SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One(SIST

SCSI Registers 4-79• Data Overflow – writing too many bytes to the SCSIFIFO, or the synchronous offset causes overwritingthe SCSI FIFO.• Offset Underf

4-80 Registersregister) must be set for this bit to become active. TheLSI53C895A always generates parity when sending SCSIdata.Register: 0x43SCSI Inte

SCSI Registers 4-81HTH Handshake-to-Handshake Timer Expired 0This bit is set when the handshake-to-handshake timerexpires. The time measured is the SC

New Features in the LSI53C895A 1-3Figure 1.2 Typical LSI53C895A Board Application1.1 New Features in the LSI53C895AThe LSI53C895A is a drop-in replace

4-82 Registerscontains the appropriate check byte at the end of theblock move. This byte must then be sent across the SCSIbus.Note: Writing any value

SCSI Registers 4-83Wide Residue message is received. It may also be anoverrun data byte. The power-up value of this register isindeterminate.Register:

4-84 RegistersRegister: 0x47General Purpose Pin Control Zero (GPCNTL0)Read/WriteThis register is used to determine if the pins controlled by the Gener

SCSI Registers 4-85GPIO GPIO Enable [1:0]These bits power-up set, causing the GPIO1 and GPIO0pins to become inputs. Clearing these bits causesGPIO[1:0

4-86 RegistersSEL[3:0] Selection Time-Out [3:0]These bits select the SCSI selection/reselection time-outperiod. When this timing (plus the 200µs selec

SCSI Registers 4-87Register: 0x49SCSI Timer One (STIME1)Read/WriteR Reserved 7HTHBA Handshake-to-Handshake Timer Bus ActivityEnable 6Setting this bit

4-88 RegistersRegister: 0x4AResponse ID Zero (RESPID0)Read/WriteRESPID0 and Response ID One (RESPID1) contain the selection orreselection IDs. In othe

SCSI Registers 4-89Register: 0x4CSCSI Test Zero (STEST0)Read OnlySSAID SCSI Selected As ID [7:4]These bits contain the encoded value of the SCSI ID th

4-90 RegistersSOM SCSI Synchronous Offset Maximum 0This bit indicates that the current synchronous SREQ/,SACK/ offset is the maximum specified by bits

SCSI Registers 4-91R Reserved [5:4]QEN SCLK Quadrupler Enable 3This bit, when set, powers up the internal clockquadrupler circuit, which quadruples th

iiThis document contains proprietary information of LSI Logic Corporation. Theinformation contained herein is not to be used by or disclosed to third

1-4 General DescriptionAdditional features of the LSI53C895A include:• Hardware control of SCSI activity LED.• Nine GPIO Pins.• 32-bit ISTAT registers

4-92 RegistersNote: Do not set this bit during normal operation, since it couldcause contention on the SCSI bus. It is included fordiagnostic purposes

SCSI Registers 4-93Note: Never set this bit during fast SCSI (greater than 5 Mbytetransfers per second) operations, because a valid assertioncould be

4-94 RegistersSTR SCSI FIFO Test Read 6Setting this bit places the SCSI core into a test mode inwhich the SCSI FIFO is easily read. Reading the leasts

SCSI Registers 4-95timers by greatly reducing all three time-out periods.Setting this bit starts all three timers and if the respectivebits in the SCS

4-96 RegistersRegisters:0x50–0x51SCSI Input Data Latch (SIDL)Read OnlySIDL SCSI Input Data Latch [15:0]This register is used primarily for diagnostic

SCSI Registers 4-97LOCK Frequency Lock 5This bit is used when enabling the SCSI clock quadrupler,which allows the LSI53C895A to transfer data at Ultra

4-98 RegistersRegister: 0x56Chip Control 0 (CCNTL0)Read/WriteENPMJ Enable Phase Mismatch Jump 7Upon setting this bit, any phase mismatches do notinter

SCSI Registers 4-99ENNDJ Enable Jump On Nondata Phase Mismatches 5This bit controls whether or not a jump is taken during anondata phase mismatch (i.e

4-100 RegistersRegister: 0x57Chip Control 1 (CCNTL1)Read/WriteZMODE High Impedance Mode 7Setting this bit causes the LSI53C895A to place all outputand

SCSI Registers 4-101Index Mode 1 (64TIMOD set) table entry format:EN64TIBMV Enable 64-Bit Table Indirect BMOV 1Setting this bit enables 64-bit address

Toler AN T®Technology 1-5transceivers. Ultra2 SCSI with LVD allows a longer SCSI cable and moredevices on the bus, with the same cables defined in the

4-102 RegistersRegister: 0x5AGeneral Purpose Pin Control One (GPCNTL1)Read/WriteThis register is used to determine if the signals controlled by the Ge

SCSI Registers 4-103Registers:0x5C–0x5FScratch Register B (SCRATCHB)Read/WriteSCRATCHB Scratch Register B [31:0]This is a general purpose user definab

4-104 Registers4.3 64-Bit SCRIPTS SelectorsThe following registers are used to hold the upper 32-bit addresses forvarious SCRIPTS operations. When a p

64-Bit SCRIPTS Selectors 4-105Writes to the MMRS register are unaffected. Clearing thePCI Configuration Into Enable bit causes the MMRSregister to ret

4-106 Registersregister return the PCI Revision ID (Rev ID) register valueand bits [15:0] return the PCI Device ID register valuewhen read.Writes to t

64-Bit SCRIPTS Selectors 4-107Registers:0xB4–0xB7Dynamic Block Move Selector (DBMS)Read/WriteDBMS Dynamic Block Move Selector [31:0]Supplies the upper

4-108 Registers4.4 Phase Mismatch Jump RegistersEight 32-bit registers contain the byte count and addressing informationrequired to update the direct,

Phase Mismatch Jump Registers 4-109Registers:0xC4–0xC7PhaseMismatchJumpAddress2(PMJAD2)Read/WritePMJAD2 Phase Mismatch Jump Address 2 [31:0]This regis

4-110 RegistersmemorywiththeexceptionofapossiblebyteintheSWIDE register. That byte must be flushed to memorymanually in SCRIPTS.In the case of a SCSI

Phase Mismatch Jump Registers 4-111Registers:0xD0–0xD3Entry Storage Address (ESA)Read/WriteESA Entry Storage Address [31:0]This register's value

1-6 General Description1.5 LSI53C895A Benefits SummaryThis section of the chapter provides an overview of the LSI53C895Afeatures and benefits. It cont

4-112 RegistersRegisters:0xD8–0xDASCSI Byte Count (SBC)Read onlySBC SCSI Byte Count [23:0]This register contains the count of the number of bytestrans

Phase Mismatch Jump Registers 4-113the SCSI bus during data phases, i.e. it will not countbytes sent in command, status, message in or messageout phas

4-114 Registers

LSI53C895A PCI to Ultra2 SCSI Controller 5-1Chapter 5SCSI SCRIPTSInstruction SetThe LSI53C895A contains a SCSI SCRIPTS processor that permits bothDMA

5-2 SCSI SCRIPTS Instruction Setrequire certain unique timings or bus sequences to operate properly.Another feature allowed at the low level is loopba

High Level SCSI SCRIPTS Mode 5-3Each instruction consists of two or three 32-bit words. The first 32-bitword is always loaded into the DMA Command (DC

5-4 SCSI SCRIPTS Instruction Set• The LSI53C895A typically fetches two Dwords (64 bits) and decodesthe high order byte of the first longword as a SCRI

Block Move Instruction 5-5Figure 5.1 SCRIPTS Overview5.3 Block Move InstructionPerforming a Block Move instruction, bit 5, Source I/O - Memory Enable(

5-6 SCSI SCRIPTS Instruction Set5.3.1 First DwordIT[1:0] Instruction Type - Block Move [31:30]The IT bit configuration (00) defines a Block MoveInstru

Block Move Instruction 5-7Once the data pointer address is loaded, it is executedas when the chip operates in the direct mode. Thisindirect feature al

LSI53C895A Benefits Summary 1-7• Performs sustained memory-to-memory DMA transfers toapproximately 100 Mbytes/s.• Minimizes SCSI I/O start latency.• P

5-8 SCSI SCRIPTS Instruction SetAfter a Table Indirect opcode is fetched, the DSA isadded to the 24-bit signed offset value from the opcodeto generate

Block Move Instruction 5-9These instructions perform the following steps:1. The LSI53C895A verifies that it is connected to the SCSIbus as a Target be

5-10 SCSI SCRIPTS Instruction Set(SWIDE) register during a receive operation. This byte iscombined with the first byte from the subsequent transferso

Block Move Instruction 5-11or in the SCSI Output Data Latch (SODL) register during asend operation. This byte is combined with the first bytefrom the

5-12 SCSI SCRIPTS Instruction SetTC[23:0] Transfer Counter [23:0]This 24-bit field specifies the number of data bytes to bemoved between the LSI53C895

I/O Instruction 5-135.4 I/O InstructionI/O Instructions perform the following SCSI operations in Target andInitiator mode. These I/O operations are ch

5-14 SCSI SCRIPTS Instruction SetTarget ModeReselect InstructionThe LSI53C895A arbitrates for the SCSI bus by assertingthe SCSI ID stored in the SCSI

I/O Instruction 5-15If reselected, the LSI53C895A fetches the next instructionfrom the address pointed to by the 32-bit jump addressfield stored in th

5-16 SCSI SCRIPTS Instruction SetInitiator ModeSelect InstructionThe LSI53C895A arbitrates for the SCSI bus by assertingthe SCSI ID stored in the SCSI

I/O Instruction 5-17Wait Reselect InstructionIf the LSI53C895A is selected before being reselected, itfetches the next instruction from the address po

1-8 General Description1.5.3 IntegrationFeatures of the LSI53C895A which ease integration include:• High-performance SCSI core.• Integrated LVD transc

5-18 SCSI SCRIPTS Instruction SetData Structure Address (DSA) register, and used as anoffset relative to the value in the Data Structure Address(DSA)

I/O Instruction 5-19DirectUses the device ID and physical address in theinstruction.Table IndirectUses the physical jump address, but fetches data usi

5-20 SCSI SCRIPTS Instruction Setthis bit for the Select instruction. If this bit is set on anyother I/O instruction, an illegal instruction interrupt

I/O Instruction 5-21Since SACK/ and SATN/ are Initiator signals, they are notasserted on the SCSI bus unless the LSI53C895A isoperating as an Initiato

5-22 SCSI SCRIPTS Instruction Set5.5 Read/Write InstructionsThe Read/Write instruction supports addition, subtraction, andcomparison of two separate v

Read/Write Instructions 5-23A[6:0] Register Address - A[6:0] [22:16]It is possible to change register values from SCRIPTS inread-modify-write cycles o

5-24 SCSI SCRIPTS Instruction Set5.5.4 Move To/From SFBR CyclesAll operations are read-modify-writes. However, two registers areinvolved, one of which

Read/Write Instructions 5-25Miscellaneous Notes:• Substitute the desired register name or address for “RegA” in the syntax examples.• data8 indicates

5-26 SCSI SCRIPTS Instruction Set5.6 Transfer Control InstructionsThis section describes the Transfer Control Instructions. Theconfiguration of the Op

Transfer Control Instructions 5-27Jump InstructionThe LSI53C895A can do a true/false comparison of theALU carry bit, or compare the phase and/or data

LSI53C895A Benefits Summary 1-91.5.5 FlexibilityThe LSI53C895A provides:• Universal LVD transceivers are backward compatible with SE or HVDdevices.• H

5-28 SCSI SCRIPTS Instruction SetWhen a Return instruction is executed, the value storedin the Temporary (TEMP) register is returned to the DSPregiste

Transfer Control Instructions 5-29valid when the LSI53C895A is operating in Initiator mode.Clear these bits when the LSI53C895A is operating inTarget

5-30 SCSI SCRIPTS Instruction SetThe SCRIPTS program counter is a 32-bit value pointingto the SCRIPTS currently under execution by theLSI53C895A. The

Transfer Control Instructions 5-31CD Compare Data 18When this bit is set, the first byte received from the SCSIdata bus (contained in the SCSI First B

5-32 SCSI SCRIPTS Instruction SetDCV Data Compare Value [7:0]This 8-bit field is the data compared against the register.These bits are used in conjunc

Memory Move Instructions 5-33• Indirect addresses are not allowed. A burst of data is fetched fromthe source address, put into the DMA FIFO and then w

5-34 SCSI SCRIPTS Instruction Set5.7.2 Read/Write System Memory from SCRIPTSBy using the Memory Move instruction, single or multiple register valuesar

Load and Store Instructions 5-355.7.4 Third DwordTEMP Register [31:0]These bits contain the destination address for theMemory Move.5.8 Load and Store

5-36 SCSI SCRIPTS Instruction SetThe SIOM and DIOM bits in the DMA Mode (DMODE) register determinewhether the destination or source address of the ins

Load and Store Instructions 5-37Note: This bit has no effect unless the Prefetch Enable bit in theDMA Control (DCNTL) register is set.LS Load and Stor

1-10 General Description• Power and ground isolation of I/O pads and internal chip logic.• TolerANT technology, which provides:– Active negation of SC

5-38 SCSI SCRIPTS Instruction Set

LSI53C895A PCI to Ultra2 SCSI Controller 6-1Chapter 6ElectricalSpecificationsThis section specifies the LSI53C895A electrical and mechanicalcharacteri

6-2 Electrical SpecificationsTable 6.1 Absolute Maximum Stress RatingsSymbol Parameter Min Max Unit Test ConditionsTSTGStorage temperature −55 150 °C–

DC Characteristics 6-3Figure 6.1 LVD DriverTable 6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SREQ2/, SACK/,SACK2/, SMSG/, SIO/, SCD/, SAT

6-4 Electrical SpecificationsFigure 6.2 LVD ReceiverVCM+−+++−−−VI2VI2Table 6.5 DIFFSENS SCSI SignalSymbol Parameter Min Max Unit Test Conditions11. Fu

DC Characteristics 6-5Table 6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/Symbol Parameter Min Max Unit Test ConditionsVIHInput high

6-6 Electrical SpecificationsTable 6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/,DEVSEL/,STOP/,PERR/,PARSymbol Parameter Min Ma

DC Characteristics 6-7Table 6.11 Output Signal—TDOSymbol Parameter Min Max Unit Test ConditionsVOHOutput high voltage 2.4 VDDV −4mAdynamicVOLOutput lo

6-8 Electrical Specifications6.2 TolerANT Technology Electrical CharacteristicsThe LSI53C895A features TolerANT technology, which includes activenegat

TolerANT Technology Electrical Characteristics 6-9Figure 6.3 Rise and Fall Time Test ConditionFigure 6.4 SCSI Input FilteringtFFall time, 90% to 10% 4

LSI53C895A PCI to Ultra2 SCSI Controller 2-1Chapter 2Functional DescriptionChapter 2 is divided into the following sections:• Section 2.1, “PCI Functi

6-10 Electrical SpecificationsFigure 6.5 Hysteresis of SCSI ReceiversFigure 6.6 Input Current as a Function of Input Voltage1Receiving Logic Level01.1

TolerANT Technology Electrical Characteristics 6-11Figure 6.7 Output Current as a Function of Output VoltageOutput Sink Current (milliAmperes)0−200−40

6-12 Electrical Specifications6.3 AC CharacteristicsThe AC characteristics described in this section apply over the entirerange of operating condition

AC Characteristics 6-13Table 6.16 and Figure 6.9 provide Reset Input timing data.Figure 6.9 Reset InputTable 6.16 Reset InputSymbol Parameter Min Max

6-14 Electrical SpecificationsTable 6.17 and Figure 6.10 provide Interrupt Output timing data.Figure 6.10 Interrupt Output6.4 PCI and External Memory

PCI and External Memory Interface Timing Diagrams 6-15– 32-Bit Operating Register/SCRIPTS RAM Write– 64-Bit Address Operating Register/SCRIPTS RAM Wri

6-16 Electrical SpecificationsFigure 6.11 PCI Configuration Register ReadTable 6.18 PCI Configuration Register ReadSymbol Parameter Min Max Unitt1Shar

PCI and External Memory Interface Timing Diagrams 6-17Figure 6.12 PCI Configuration Register WriteTable 6.19 PCI Configuration Register WriteSymbol Pa

6-18 Electrical SpecificationsFigure 6.13 32-Bit Operating Register/SCRIPTS RAM ReadTable 6.20 32-Bit Operating Register/SCRIPTS RAM ReadSymbol Parame

PCI and External Memory Interface Timing Diagrams 6-19Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM ReadTable 6.21 64-Bit Address Operatin

2-2 Functional DescriptionFigure 2.1 LSI53C895A Block Diagram2.1 PCI Functional DescriptionThe LSI53C895A implements a PCI-to-Wide Ultra2 SCSI control

6-20 Electrical SpecificationsFigure 6.15 32-Bit Operating Register/SCRIPTS RAM WriteTable 6.22 32-Bit Operating Register/SCRIPTS RAM WriteSymbol Para

PCI and External Memory Interface Timing Diagrams 6-21Figure 6.16 64-Bit Address Operating Register/SCRIPTS RAM WriteTable 6.23 64-Bit Address Operati

6-22 Electrical Specifications6.4.2 Initiator TimingTables 6.24 through 6.31 and Figures 6.17 and 6.24 describe Initiatortiming.Table 6.24 Nonburst Op

PCI and External Memory Interface Timing Diagrams 6-23Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by

6-24 Electrical SpecificationsTable 6.25 Burst Opcode Fetch, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 –

PCI and External Memory Interface Timing Diagrams 6-25Figure 6.18 Burst Opcode Fetch, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI

6-26 Electrical SpecificationsTable 6.26 Back to Back Read, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 – n

PCI and External Memory Interface Timing Diagrams 6-27Figure 6.19 Back to Back Read, 32-Bit Address and DataCLK(Driven by System)FRAME/(Driven by LSI5

6-28 Electrical SpecificationsTable 6.27 Back to Back Write, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 –

PCI and External Memory Interface Timing Diagrams 6-29Figure 6.20 Back to Back Write, 32-Bit Address and Datat9t4t3CLK(Driven by System)GPIO0_FETCH/(D

PCI Functional Description 2-32.1.1.1 Configuration SpaceThe host processor uses the PCI configuration space to initialize theLSI53C895A through a def

6-30 Electrical SpecificationsTable 6.28 Burst Read, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 – nst2Shar

PCI and External Memory Interface Timing Diagrams 6-31Figure 6.21 Burst Read, 32-Bit Address and Datat1t2CLKGPIO0_FETCH/(Driven by LSI53C895A)GPIO1_MA

6-32 Electrical SpecificationsTable 6.29 Burst Read, 64-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 – nst2Shar

PCI and External Memory Interface Timing Diagrams 6-33Figure 6.22 Burst Read, 64-Bit Address and Datat1CLK(Driven by System)GPIO0_FETCH/(Driven by LSI

6-34 Electrical SpecificationsTable 6.30 Burst Write, 32-Bit Address and DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 – nst2Sha

PCI and External Memory Interface Timing Diagrams 6-35Figure 6.23 Burst Write, 32-Bit Address and Datat1CLK(Driven by System)GPIO0_FETCH/(Driven by LS

6-36 Electrical SpecificationsTable 6.31 Burst Write, 64-Bit Address and 32-Bit DataSymbol Parameter Min Max Unitt1Shared signal input setup time 7 –

PCI and External Memory Interface Timing Diagrams 6-37Figure 6.24 Burst Write, 64-Bit Address and 32-Bit Datat1CLK(Driven by System)GPIO0_FETCH/(Drive

6-38 Electrical SpecificationsThis page intentionally left blank.

PCI and External Memory Interface Timing Diagrams 6-396.4.3 External Memory TimingTables 6.32 through 6.39 and Figures 6.25 through 6.34 describeExter

Preface iiiPrefaceThis book is the primary reference and technical manual for theLSI53C895A PCI to Ultra2 SCSI Controller. It contains a completefunct

2-4 Functional Description2.1.2 PCI Bus Commands and Functions SupportedBus commands indicate to the target the type of transaction the masteris reque

6-40 Electrical SpecificationsFigure 6.25 External Memory Read12 3 4 56 7 8 9CLK(Driven by System)PAR(Driven by Master-Addr;IRDY/(Driven by Master)TRD

PCI and External Memory Interface Timing Diagrams 6-41Figure 6.25 External Memory Read (Cont.)MAD(Addr driven by LSI53C895A;Data driven by Memory)11 1

6-42 Electrical SpecificationsThis page intentionally left blank.

PCI and External Memory Interface Timing Diagrams 6-43Table 6.33 External Memory WriteSymbol Parameter Min Max Unitt1Shared signal input setup time 7

6-44 Electrical SpecificationsFigure 6.26 External Memory WriteCLK(Driven by System)PA RIRDY/(Driven by Master)TRDY/(Driven by LSI53C895A)STOP/(Driven

PCI and External Memory Interface Timing Diagrams 6-45Figure 6.26 External Memory Write (Cont.)CLK(Driven by System)PA RIRDY/(Driven by Master)TRDY/(D

6-46 Electrical SpecificationsFigure 6.27 Normal/Fast Memory (≥= 128 Kbytes) Single Byte Access Read CycleTable 6.34 Normal/Fast Memory (≥= 128 Kbytes

PCI and External Memory Interface Timing Diagrams 6-47Figure 6.28 Normal/Fast Memory (≥= 128 Kbytes) Single Byte Access Write CycleTable 6.35 Normal/F

6-48 Electrical SpecificationsFigure 6.29 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Read CycleMAD(Addr Driven by LSI53C895A;MAS1/(Driven

PCI and External Memory Interface Timing Diagrams 6-49Figure 6.29 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Read Cycle(Cont.)MAD(Addr Dr

PCI Functional Description 2-52.1.2.2 Special Cycle CommandThe LSI53C895A does not respond to this command as a slave and itnever generates this comma

6-50 Electrical SpecificationsFigure 6.30 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Write CycleCLK(Driven by System)PARIRDY/(Driven by M

PCI and External Memory Interface Timing Diagrams 6-51Figure 6.30 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Write Cycle(Cont.)CLK(Driven

6-52 Electrical SpecificationsFigure 6.31 Slow Memory (≤= 128 Kbytes) Read CycleTable 6.36 Slow Memory (≤= 128 Kbytes) Read CycleSymbol Parameter Min

PCI and External Memory Interface Timing Diagrams 6-53Figure 6.32 Slow Memory (≤= 128 Kbytes) Write CycleTable 6.37 Slow Memory (≤= 128 Kbytes) Write

6-54 Electrical SpecificationsFigure 6.33 ≤ 64 Kbytes ROM Read CycleTable 6.38≤= 64 Kbytes ROM Read CycleSymbol Parameter Min Max Unitt11Address setup

PCI and External Memory Interface Timing Diagrams 6-55Figure 6.34 ≤ 64 Kbyte ROM Write CycleTable 6.39≤= 64 Kbyte ROM Write CycleSymbol Parameter Min

6-56 Electrical Specifications6.5 SCSI Timing DiagramsTables 6.40 through 6.50 and Figures 6.35 through 6.39 and describe theLSI53C895A SCSI timing.Fi

SCSI Timing Diagrams 6-57Figure 6.36 Initiator Asynchronous ReceiveTable 6.41 Initiator Asynchronous ReceiveSymbol Parameter Min Max Unitt1SACK/ asser

6-58 Electrical SpecificationsFigure 6.37 Target Asynchronous SendTable 6.42 Target Asynchronous SendSymbol Parameter Min Max Unitt1SREQ/ deasserted f

SCSI Timing Diagrams 6-59Figure 6.38 Target Asynchronous ReceiveTable 6.43 Target Asynchronous ReceiveSymbol Parameter Min Max Unitt1SREQ/ deasserted

2-6 Functional Description2.1.2.9 Configuration Write CommandThe Configuration Write command transfers data to the configurationspace of each agent. A

6-60 Electrical SpecificationsTable 6.45 SCSI-1 Transfers (Differential 4.17 Mbytes)Symbol Parameter Min Max Unitt1Send SREQ/ or SACK/ assertion pulse

SCSI Timing Diagrams 6-61Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes(16-Bit Transfers) 50 MHz Clock1, 21. Transfer p

6-62 Electrical SpecificationsTable 6.49 Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes (8-Bit Transfers)or 40.0 Mbytes (16-Bit Transfers)

SCSI Timing Diagrams 6-63Figure 6.39 Initiator and Target Synchronous TransferTable 6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 M

6-64 Electrical Specifications6.6 Package DiagramsThis section provides pinout information for both chips. Figure 6.40 ispinout information for the LS

Package Diagrams 6-65Figure 6.40 LSI53C895A 272-Pin BGA Top ViewA1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20VSS N/C SD2+ SD3

6-66 Electrical SpecificationsTable 6.51 272 BGA Pin List by LocationIDSEL V6AD21 V7AD18 V8FRAME/ V9NC V10PERR/ V11AD15 V12AD12 V13NC V14NC V15NC V16A

Package Diagrams 6-67Table 6.52 BGA Pin List AlphabeticallyVDD D11VDD D15VDD F4VDD F17VDD K4VDD L17VDD R4VDD R17VDD U6VDD U10VDD U15VDDRBIAS A11VDDA H

6-68 Electrical SpecificationsFigure 6.41 LSI53C895A 208-Pin Plastic Quad Flat PackALT_IRQ/AD26AD25VSSPCIAD22AD19AD17VSSPCIIRDY/DEVSEL/STOP/PERR/AD14A

Package Diagrams 6-69Table 6.53 Signal Names vs. Pin Number: 208-Pin Plastic Quad Flat PackVDDIO 73VDDIO 81VDDIO 184VDDPCI 2VDDPCI 13VDDPCI 23VDDPCI 2

PCI Functional Description 2-72.1.2.11 Dual Address Cycle (DAC) CommandThe LSI53C895A performs DACs when 64-bit addressing is required.Refer to the PC

6-70 Electrical SpecificationsThis page intentionally left blank.

Package Diagrams 6-716.6.1 LSI53C895A vs. LSI53C895 Pin/Ball DifferencesThe LSI53C895A can be used as a drop-in replacement for theLSI53C895. The LSI5

6-72 Electrical SpecificationsTable 6.54 indicates the differences between the LSI53C895A and theLSI53C895 signal names and locations.Table 6.54 LSI53

Package Diagrams 6-73LSI Logic component dimensions conform to a current revision of theJEDEC Publication 95 standard package outline, using ANSI 14.5

6-74 Electrical SpecificationsFigure 6.42 is the mechanical drawing for the 208 PQFP and Figure 6.43is the mechanical drawing for the 272 PBGA for the

Package Diagrams 6-75Figure 6.42 208-Pin PQFP (P9) Mechanical Drawing (Sheet 2 of 2)Important: This drawing may not be the latest version. For board l

6-76 Electrical SpecificationsFigure 6.43 LSI53C895A 272 PBGA Mechanical DrawingImportant: This drawing may not be the latest version. For board layou

LSI53C895A PCI to Ultra2 SCSI Controller A-1Appendix ARegister SummaryTable A.1 lists the PCI register summary by register name for theLSI53C895A.Tabl

A-2 Register SummaryTable A.2 lists the SCSI register summary by register name for theLSI53C895A.Min_Gnt 0x3E Read Only 4-14Next Item Pointer 0x41 Rea

Register Summary A-3Chip Test Two ( CT EST2) 0x1A Re ad Only (bit 3write)4-55Chip Test Zero (CTEST0) 0x18 Read/Write 4-54Cumulative SCSI Byte Count (C

2-8 Functional DescriptionIf the Read Multiple mode is enabled and the Read Line mode isdisabled, Read Multiple commands are issued if the Read Multip

A-4 Register SummaryMailbox One (MBOX1) 0x17 Read/Write 4-53Mailbox Zero (MBOX0) 0x16 Read/Write 4-53Memory Access Control (MACNTL) 0x46 Read/Write 4-

Register Summary A-5SCSI Control Two (SCNTL2) 0x02 Read/Write 4-27SCSI Control Zero (SCNTL0) 0x00 Read/Write 4-21SCSI Destination ID (SDID) 0x06 Read/

A-6 Register SummarySCSI Timer Zero (STIME0) 0x48 Read/Write 4-85SCSI Transfer (SXFER) 0x05 Read/Write 4-32SCSI Wide Residue (SWIDE) 0x45 Read/Write 4

LSI53C895A PCI to Ultra2 SCSI Controller B-1Appendix BExternal MemoryInterface DiagramExamplesAppendix B has example external memory interface diagram

B-2 External Memory Interface Diagram ExamplesFigure B.2 64 Kbyte Interface with 150 ns MemoryLSI53C895A27C512-15/MOE/OEMCE/CED08MAD[7:0]BusCKQ08A[7:0

External Memory Interface Diagram Examples B-3Figure B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 nsMemoryLSI53C895A27C020-15

B-4 External Memory Interface Diagram ExamplesFigure B.4 512 Kbyte Interface with 150 ns MemoryOEWED[7:0]A0A16...LSI53C895AMOE/8MAD[7:0]BusA[7:0]D0CKQ

LSI53C895A PCI to Ultra2 SCSI Controller IX-1IndexSymbols(64TIMOD) 4-100(A7) 5-23(AAP) 4-23(ABRT) 4-41, 4-48(ACK) 4-38, 4-40(ADB) 4-24(ADCK) 4-62(ADDE

IX-2 Index(EPC) 4-23(EPER) 4-4(ERBA) 4-12(ERL) 4-69(ERMP) 4-69(ESA) 4-111(EWS) 4-30(EXC) 4-24(EXT) 4-92(FBL3) 4-60(FE) 4-84(FF[3:0]) 4-44(FF4) 4-47(FF

Index IX-3(SDU) 4-27(SE) 4-4(SEL) 4-38, 4-40, 4-75, 4-78(SEL[3:0]) 4-86(SEM) 4-50(SFBR) 4-37(SFS) 4-105(SGE) 4-75, 4-78(SI) 4-52(SID) 4-11(SIDA) 4-18(

PCI Functional Description 2-9(DMODE) burst size bits, and Chip Test Five (CTEST5), bit2.Ifmultiplecache line size transfers are not desired, set the

IX-4 IndexBbase address registerone (BAR1) 2-3, 4-9two (BAR2) 4-10zero - I/O (BAR0) 4-9bidirectional 3-3signals 6-5BIOS 2-3bits used for parity contro

Index IX-5disable (Cont.)halt on parity error or ATN (target only) (DHP) 4-24internal load and store (DILS) 4-99single initiator response (DSI) 4-94di

IX-6 IndexGPIO5 3-10GPIO6 3-10GPIO7 3-10GPIO8 3-10grant 3-8Hhalt SCSI clock (HSC) 4-94halting 2-48handshake-to-handshake timerbus activity enable (HTH

Index IX-7MMAC/_TESTOUT 3-14MADbus 2-56bus programming 3-19pins 2-56MAD[0] 3-20MAD[3:1] 3-20MAD[4] 3-19MAD[5] 3-19MAD[6] 3-19MAD[7:0] 3-15MAD[7:0] pin

IX-8 Indexpower (Cont.)state D0 2-61state D1 2-61state D2 2-62state D3 2-62power state (PWS[1:0]) 4-17prefetchenable (PFEN) 4-72flush 2-24flush (PFF)

Index IX-9SCSI (Cont.)interrupt status zero (SIST0) 4-77interrupts 2-48isolation mode (ISO) 4-90longitudinal parity (SLPAR) 4-81loopback mode 2-26loop

IX-10 Indexstart (Cont.)SCSI transfer (SST) 4-26sequence (START) 4-22static block move selector (SBMS) 4-106STEST2 register 2-26STOP command 2-9stop s

LSI53C895A PCI to Ultra2 SCSI ControllerCustomer FeedbackWe would appreciate your feedback on this document. Please copy thefollowing page, add your c

Customer FeedbackReader’s CommentsFax your comments to: LSI Logic CorporationTechnical PublicationsM/S E-198Fax: 408.433.4333Please tell us how you ra

U.S. Distributorsby StateA. E. Avnet Electronicshttp://www.hh.avnet.comB. M. Bell Microproducts,Inc. (for HAB’s)http://www.bellmicro.comI. E. Insight

2-10 Functional Descriptionaddresses corresponding to cache line boundaries. In conjunction withthe CacheLineSizeregister, the PCI commands Memory Rea

U.S. Distributorsby State(Continued)New YorkHauppaugeI. E. Tel: 516.761.0960Long IslandA. E. Tel: 516.434.7400W. E. Tel: 800.861.9953RochesterA. E. Te

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Sales Offices and DesignResource CentersLSI Logic CorporationCorporate Headquarters1551 McCarthy BlvdMilpitas CA 95035Tel: 408.433.8000Fax: 408.433.89

Sales Offices and DesignResource Centers(Continued)KoreaSeoulLSI Logic Corporation ofKorea Ltd10th Fl., Haesung 1 Bldg.942, Daechi-dong,Kangnam-ku, Se

International DistributorsAustraliaNew South WalesReptechnic Pty Ltd3/36 Bydown StreetNeutral Bay, NSW 2089♦Tel: 612.9953.9844Fax: 612.9953.9683Belgiu

PCI Functional Description 2-11• To issue Memory Read Line commands, the Read Line enable bit inthe DMA Mode (DMODE) register must be set.• To issue M

2-12 Functional Description• A single Memory Write to align to a cache boundary.• Multiple Memory Write and Invalidates.• A single data residual Memor

PCI Functional Description 2-13Table 2.2 PCI Cache Mode AlignmentHost MemoryA0x00B0x040x08C0x0CD0x100x140x180x1CE0x200x240x280x2CF0x300x340x380x3CG0x4

iv Preface• Chapter 6, Electrical Specifications, contains the electricalcharacteristics and AC timing diagrams.• Appendix A, Register Summary, is a r

2-14 Functional Description2.1.3.5 Examples:The examples in this section employ the following abbreviations:MR = Memory Read, MRL = Memory Read Line,

PCI Functional Description 2-15Read Example 2 –Burst=8Dwords,CacheLineSize=4Dwords:Read Example 3 –Burst = 16 Dwords, Cache Line Size = 8 Dwords:AtoB:

2-16 Functional DescriptionWrite Example 1 –Burst=4Dwords,CacheLineSize=4Dwords:AtoB: MW (6 bytes)AtoC: MW (13 bytes)AtoD: MW (17 bytes)CtoD: MW (5 by

PCI Functional Description 2-17Write Example 2 –Burst=8Dwords,CacheLineSize=4Dwords:AtoB: MW (6 bytes)AtoC: MW (13 bytes)AtoD: MW (17 bytes)CtoD: MW (

2-18 Functional DescriptionWrite Example 3 –Burst = 16 Dwords, Cache Line Size = 8 Dwords:2.1.3.6 Memory-to-Memory MovesMemory-to-Memory Moves also su

SCSI Functional Description 2-19The LSI53C895A offers low level register access or a high-level controlinterface. Like first generation SCSI devices,

2-20 Functional DescriptionThe Phase Mismatch Jump logic powers up disabled and must beenabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, b

SCSI Functional Description 2-212.2.3 64-Bit Addressing in SCRIPTSThe LSI53C895A has a 32-bit PCI interface which provides 64-bitaddress capability in

2-22 Functional Description2.2.5 Designing an Ultra2 SCSI SystemSince Ultra2 SCSI is based on existing SCSI standards, it can useexisting driver progr

SCSI Functional Description 2-23Step 1. Set the SCLK Quadrupler Enable bit (SCSI Test One(STEST1),bit3).Step 2. Poll bit 5 of the SCSI Test Four (STES

Preface vLSI Logic World Wide Web Home Pagewww.lsilogic.comPCI Special Interest Group2575 N.E. KatherineHillsboro, OR 97214(800) 433-5177; (503) 693-6

2-24 Functional Descriptionflushes its contents and loads the modified code every time aninstruction is issued. To avoid inadvertently flushing the pr

SCSI Functional Description 2-25to the Data Structure Address (DSA) register. Load and Store datatransfers to or from the SCRIPTS RAM will remain inte

2-26 Functional Description2.2.10 SCSI Loopback ModeThe LSI53C895A loopback mode allows testing of both initiator andtarget functions and, in effect,

SCSI Functional Description 2-27Table 2.3 Bits Used for Parity Control and GenerationBit Name Location DescriptionAssert SATN/ onParity ErrorsSCSI Con

2-28 Functional DescriptionTable 2.4 SCSI Parity ControlEPC11. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0)).ASEP22. ASEP = Assert S

SCSI Functional Description 2-29Figure 2.2 Parity Checking/Generation2.2.12 DMA FIFOThe DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO i

2-30 Functional DescriptionFigure 2.3 DMA FIFO SectionsThe LSI53C895A automatically supports misaligned DMA transfers. A944-byte FIFO allows the LSI53

SCSI Functional Description 2-31Figure 2.4 LSI53C895A Host Interface SCSI Data PathsThe following steps determine if any bytes remain in the data path

2-32 Functional DescriptionByte Offset Counter, which consists of bits [1:0] in the CTEST5register and bits [7:0] of the DMA FIFO register. AND the re

SCSI Functional Description 2-33accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register,then the least significant byte or the most significant

vi Preface

2-34 Functional DescriptionFive (CTEST5) register and bits [7:0] of the DMA FIFO register.AND the result with 0x3FF for a byte count between zero and9

SCSI Functional Description 2-35The LSI Logic LVDlink transceivers operate in LVD or SE modes. Theyallow the chip to detect a HVD signal when the chip

2-36 Functional DescriptionACK−,MSG−,C_D−, I/O−,ATN−,SD[7:0]−, and SDP0− lines is 680 Ωwhen the Active Negation portion of LSI Logic TolerANT technolo

SCSI Functional Description 2-37Figure 2.5 8-Bit HVD Wiring Diagram for Ultra2 SCSILSI53C8XXSEL+BSY+RST+SEL−BSY−RST−REQ−ACK−MSG−C/D−I/O−ATN −REQ−ACK+S

2-38 Functional Description2.2.13.3 SCSI TerminationThe terminator networks provide the biasing needed to pull signals to aninactive voltage level, an

SCSI Functional Description 2-39Figure 2.6 Regulated Termination for Ultra2 SCSI2.2.14 Select/Reselect During Selection/ReselectionIn multithreaded SC

2-40 Functional DescriptionStatus Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers,respectively, indicating that the LSI53C895A has been

SCSI Functional Description 2-41Figure 2.7 Determining the Synchronous Transfer Rate2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0

2-42 Functional Description2.2.15.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0])The CCF[2:0] bits select the factor by which the freque

SCSI Functional Description 2-432.2.16 Interrupt HandlingThe SCRIPTS processors in the LSI53C895A perform most functionsindependently of the host micr

Contents viiContentsChapter 1 General Description1.1 New Features in the LSI53C895A 1-31.2 Benefits of Ultra2 SCSI 1-41.3 Benefits of LVDlink 1-41.4 T

2-44 Functional DescriptionThe host (C Code) or the SCRIPTS code could potentially try to accessthe mailbox bits at the same time.If the SIP bit in th

SCSI Functional Description 2-45If the DFE bit is cleared, then the FIFOs must be cleared by setting theCLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO)

2-46 Functional Descriptionchip’s behavior when the SATN/ interrupt is enabled during Target modeoperation. The Interrupt-on-the-Fly interrupt is also

SCSI Functional Description 2-47interrupt condition occurs, the SCRIPTS halt and the system neverknows it unless it times out and checks the ISTAT reg

2-48 Functional Descriptionoccur but are not stacked. These could be multiple SCSI interrupts (SIPset), multiple DMA interrupts (DIP set), or multiple

SCSI Functional Description 2-492.2.16.7 Sample Interrupt Service RoutineThe following is a sample of an interrupt service routine for theLSI53C895A.

2-50 Functional Description2.2.17 Interrupt RoutingThis section documents the recommended approach to RAID readyinterrupt routing for the LSI53C895A.

SCSI Functional Description 2-51The first option is to have the LSI53C895A load its PCI Subsystem IDusing a serial EPROM on power-up. If bit 15 in thi

2-52 Functional DescriptionFigure 2.8 Block Move and Chained Block Move InstructionsCHMOV 5, 3 when Data_OutMoves five bytes from address 0x03 in the

SCSI Functional Description 2-53(this flag is not set if a normal Block Move instruction is used). Under thiscondition, the SCSI controller does not s

viii Contents2.2.10 SCSI Loopback Mode 2-262.2.11 Parity Options 2-262.2.12 DMA FIFO 2-292.2.13 SCSI Bus Interface 2-342.2.14 Select/Reselect During S

2-54 Functional Description2.2.18.4 SODL RegisterFor send data, the low-order byte of the SCSI Output Data Latch (SODL)register holds the low-order by

Parallel ROM Interface 2-55transferred from memory but not to the SCSI bus when a partial transferexists. For example, if the instruction is an Initia

2-56 Functional DescriptionThe LSI53C895A supports a variety of sizes and speeds of expansionROM, using pull-down resistors on the MAD[3:0] pins. The

Serial EEPROM Interface 2-572.4 Serial EEPROM InterfaceThe LSI53C895A implements an interface that allows attachment of aserial EEPROM device to the G

2-58 Functional Description2.4.2 No Download ModeWhen MAD7 is pulled up through an external resistor, the automaticdownload is disabled and no data is

Alternative SSVID/SSID Loading Mechanism 2-59An additional register, the Subsystem ID Access, is located in the PCIconfiguration space at offset 0x48–

2-60 Functional DescriptionEEPROM value is always the first value loaded (if that mechanism isenabled). The system would then have the opportunity to

Power Management 2-61The LSI53C895A power states shown in Ta ble 2. 9 are independentlycontrolled through two power state bits that are located in the

2-62 Functional Description2.6.3 Power State D2Power state D2 is a lower power state than D1. In this state theLSI53C895A core is placed in the coma m

LSI53C895A PCI to Ultra2 SCSI Controller 3-1Chapter 3Signal DescriptionsThis chapter presents the LSI53C895A pin configuration and signaldefinitions u

Contents ix3.6 Test Interface Signals 3-163.7 Power and Ground Signals 3-173.8 MAD Bus Programming 3-19Chapter 4 Registers4.1 PCI Configuration Regist

3-2 Signal Descriptions3.1 LSI53C895A Functional Signal GroupingFigure 3.1 presents the LSI53C895A signals by functional group.Figure 3.1 LSI53C895A F

Signal Descriptions 3-33.2 Signal DescriptionsThe Signal Descriptions are divided into PCI Bus Interface Signals, SCSIBus Interface Signals, Flash ROM

3-4 Signal Descriptions3.3 PCI Bus Interface SignalsThe PCI Bus Interface Signals section contains tables describing thesignals for the following sign

PCI Bus Interface Signals 3-53.3.2 Address and Data SignalsTable 3.3 describes Address and Data signals.Table 3.3 Address and Data SignalsName PQFP BG

3-6 Signal Descriptions3.3.3 Interface Control SignalsTable 3.4 describes the Interface Control signals.PAR 30 Y12 T/S 8 mA P CI Parity is the even pa

PCI Bus Interface Signals 3-7IRDY/ 22 W9 S/T/S 8 mA PCI Initiator Ready indicates theinitiating agent’s (bus master’s)ability to complete the current

3-8 Signal Descriptions3.3.4 Arbitration SignalsTable 3.5 describes Arbitration signals.3.3.5 Error Reporting SignalsTable 3.6 describes the Error Rep

PCI Bus Interface Signals 3-93.3.6 Interrupt SignalsTable 3.7 describes the Interrupt signals.Table 3.7 Interrupt SignalsName PQFP BGA Pos Type Streng

3-10 Signal Descriptions3.3.7 SCSIGPIOSignalsTable 3.8 describes the SCSI GPIO signals.Table 3.8 SCSI GPIO SignalsName PQFP BGA Pos Type Strength Desc

SCSI Bus Interface Signals 3-113.4 SCSI Bus Interface SignalsThe SCSI Bus Interface signals section contains tables describing thesignals for the foll