Avago-technologies LSI53C1000R Manuel d'utilisateur
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®
DB14-000152-04
LSI53C1000R
PCI to Ultra160
SCSI Controller
TECHNICAL
MANUAL
August 2003
Version 2.2
- LSI53C1000R 1
- PCI to Ultra160 1
- SCSI Controller 1
- TECHNICAL 1
- Preface iii 3
- Contents 7
- Contents ix 9
- Chapter 1 19
- Introduction 19
- 1-2 Introduction 20
- General Description 1-3 21
- 1.2 Benefits of Ultra160 SCSI 22
- Technology 23
- 1.5 Benefits of TolerANT 24
- 1.6.1 SCSI Performance 25
- 1.6.2 PCI Performance 26
- 1.6.3 Integration 27
- 1.6.4 Ease of Use 27
- 1.6.5 Flexibility 28
- 1.6.6 Reliability 29
- 1.6.7 Testability 29
- 1-12 Introduction 30
- Chapter 2 31
- Functional Description 31
- 8 Kbyte SCRIPTS RAM 32
- 2.1.1 PCI Addressing 33
- 2-4 Functional Description 34
- 2-6 Functional Description 36
- 2-8 Functional Description 38
- • The following bits are set: 39
- 2-10 Functional Description 40
- 2.1.3 PCI Cache Mode 41
- 2-12 Functional Description 42
- 2.1.3.5 Examples 44
- 2-18 Functional Description 48
- 2.2.1 SCRIPTS Processor 49
- 2.2.2 Internal SCRIPTS RAM 50
- 2-22 Functional Description 52
- 2-26 Functional Description 56
- are set for 57
- 2-30 Functional Description 60
- • On every Store instruction 62
- 2.2.10 Parity/CRC/AIP Options 64
- 2.2.11 DMA FIFO 66
- 2.2.12 SCSI Data Paths 67
- 2-38 Functional Description 68
- 2.2.13 SCSI Bus Interface 69
- 2-40 Functional Description 70
- 2.2.15 Synchronous Operation 71
- 2-44 Functional Description 74
- 2.2.16 Interrupt Handling 75
- 2-46 Functional Description 76
- 2-48 Functional Description 78
- 2-50 Functional Description 80
- before halting 81
- 2.2.17 Interrupt Routing 83
- 2-54 Functional Description 84
- 2.2.18 Chained Block Moves 85
- 2-56 Functional Description 86
- 2.3 Parallel ROM Interface 88
- 2.4 Serial EEPROM Interface 90
- 2.5 Power Management 91
- 2.5.1 Power State D0 92
- 2.5.2 Power State D1 92
- 2.5.3 Power State D2 93
- 2.5.4 Power State D3 93
- 2-64 Functional Description 94
- Chapter 3 95
- Signal Descriptions 95
- Signal Organization 3-3 97
- 3.3 PCI Bus Interface Signals 99
- 3.3.4 Arbitration Signals 102
- 3.3.5 Error Reporting Signals 103
- 3.3.6 Interrupt Signals 103
- Table 3.9 SCSI Signals 104
- Table 3.11 GPIO Signals 107
- 3.7 Test Interface Signals 109
- 3.8 Power and Ground Signals 110
- 3.9 MAD Bus Programming 111
- Chapter 4 113
- Registers 113
- Registers:0x00–0x01 114
- Registers:0x02–0x03 115
- Registers:0x04–0x05 115
- 4-4 Registers 116
- Registers:0x06–0x07 117
- Register: 0x08 118
- Registers:0x09–0x0B 119
- Register: 0x0C 119
- Register: 0x0D 120
- Register: 0x0E 120
- Register: 0x0F 121
- Registers:0x10–0x13 121
- Registers:0x14–0x17 121
- Registers:0x18–0x1B 122
- Registers:0x1C–0x1F 122
- Registers:0x20–0x23 123
- Registers:0x24–0x27 123
- Registers:0x28–0x2B 123
- Registers:0x2C–0x2D 124
- Registers:0x2E–0x2F 125
- Registers:0x30–0x33 126
- Register: 0x34 127
- Registers:0x35–0x37 127
- Registers:0x38–0x3B 127
- Register: 0x3C 128
- Register: 0x3D 128
- Register: 0x3E 129
- Register: 0x3F 129
- Register: 0x40 130
- Register: 0x41 130
- Registers:0x42–0x43 130
- Registers:0x44–0x45 131
- Register: 0x46 132
- 4.2 SCSI Registers 133
- Table 4.2 SCSI Register Map 134
- Register: 0x00 135
- 4-24 Registers 136
- SCSI Registers 4-25 137
- 4-26 Registers 138
- Register: 0x01 139
- 4-28 Registers 140
- Register: 0x02 141
- 4-30 Registers 142
- Register: 0x03 143
- Register: 0x04 144
- Register: 0x05 145
- Register: 0x06 146
- Register: 0x07 147
- Register: 0x09 149
- Register: 0x0A 150
- Register: 0x0B 150
- 4-40 Registers 152
- SCSI Registers 4-41 153
- SCSI Registers 4-45 157
- Register: 0x14 158
- SCSI Registers 4-47 159
- • The LSI53C1000R is selected 160
- SCSI Registers 4-49 161
- Register: 0x15 162
- Register: 0x16 163
- Register: 0x17 163
- Register: 0x18 164
- Register: 0x19 164
- Register: 0x1A 165
- Register: 0x1B 166
- Register: 0x20 168
- Register: 0x21 168
- Register: 0x22 169
- Register: 0x23 170
- Registers:0x24–0x26 171
- Register: 0x27 172
- Registers:0x2C–0x2F 173
- Registers:0x34–0x37 174
- Register: 0x38 174
- 4-64 Registers 176
- Register: 0x39 177
- Register: 0x3A 178
- Register: 0x3B 178
- SCSI Registers 4-67 179
- 4-68 Registers 180
- Registers:0x3C–0x3F 181
- 4-70 Registers 182
- 4-72 Registers 184
- Register: 0x42 185
- 4-74 Registers 186
- • A SCRIPTS RAM parity error 187
- Register: 0x43 188
- Register: 0x44 189
- Register: 0x45 189
- Register: 0x47 190
- Register: 0x48 191
- Register: 0x49 193
- Register: 0x4A 194
- Register: 0x4B 195
- Register: 0x4C 195
- 4-84 Registers 196
- Register: 0x4D 197
- Register: 0x4E 198
- Register: 0x4F 199
- 4-88 Registers 200
- Registers:0x50–0x51 201
- Register: 0x52 201
- Register: 0x53 202
- Registers:0x54–0x55 202
- Register: 0x56 203
- 4-92 Registers 204
- Register: 0x57 205
- Registers:0x58–0x59 206
- Register: 0x5A 207
- Register: 0x5B 207
- Registers:0x5C–0x5F 208
- Registers:0x60–0x9F 209
- Registers:0xA0–0xA3 209
- Registers:0xA4–0xA7 210
- Registers:0xA8–0xAB 210
- Registers:0xAC–0xAF 211
- Registers:0xB0–0xB3 211
- Registers:0xB4–0xB7 212
- Registers:0xB8–0xBB 212
- Register: 0xBC 213
- 4-102 Registers 214
- Receive Rate (DT) 214
- Input Clock Rate 214
- SCF Divisor 2× 214
- 4-104 Registers 216
- SCSI Registers 4-105 217
- 4-106 Registers 218
- Table 4.4 DT Transfer Rates 219
- Register: 0xBD 225
- Register: 0xBE 225
- Register: 0xBF 226
- Registers:0xC0–0xC3 227
- Registers:0xC4–0xC7 227
- Registers:0xC8–0xCB 228
- Registers:0xCC–0xCF 229
- Registers:0xD0–0xD3 230
- Registers:0xD4–0xD7 231
- Registers:0xD8–0xDA 231
- Register: 0xDB 232
- Registers:0xDC–0xDF 232
- Registers:0xE0–0xE1 232
- Register: 0xE2 233
- Register: 0xE3 233
- Registers:0xE4–0xE7 234
- Registers:0xE8–0xEF 235
- Registers:0xF0–0xF1 236
- Registers:0xF2–0xF3 236
- Registers:0xF4–0xFF 236
- 4.3 SCSI Shadow Registers 237
- 4-130 Registers 242
- Chapter 5 243
- SCSI SCRIPTS Instruction Set 243
- SCSI SCRIPTS 5-3 245
- 5.2 Block Move Instructions 246
- Block Move Instructions 5-5 247
- Command Byte Count 247
- Lower Dword Address of Data 247
- Address of Pointer to Data 248
- Block Move Instructions 5-7 249
- Command Not Used 249
- Don’t Care Table Offset 249
- 00 Byte Count 249
- Physical Data Address 249
- OPC Instruction Defined 252
- 0 MOVE/MOVE64 252
- 1 CHMOV/CHMOV64 252
- Block Move Instructions 5-11 253
- 0 CHMOV/CHMOV64 253
- 1 MOVE/MOVE64 253
- 5.2.2 Second Dword 255
- 5.3 I/O Instructions 256
- Config ID Offset/period 00 261
- Absolute Alternate Address 262
- Command Table Offset 262
- 5.3.2 Second Dword 264
- 5.4 Read/Write Instructions 265
- 5.4.2 Second Dword 266
- 5.5.1 First Dword 269
- from the current 272
- MSG C/D I/O SCSI Phase 272
- 5.5.2 Second Dword 275
- 5.5.3 Third Dword 275
- 5.6 Memory Move Instructions 276
- Memory Move Instructions 5-35 277
- 5.6.2 Second Dword 278
- 5.6.3 Third Dword 279
- 5.7.1 First Dword 281
- 5.7.2 Second Dword 282
- Chapter 6 283
- Specifications 283
- Figure 6.2 LVD Receiver 286
- Table 6.6 Input Capacitance 286
- GPIO3, GPIO4 287
- , MWE/, TDO 287
- 6-10 Specifications 292
- 6.3 AC Characteristics 293
- Figure 6.9 Reset Input 294
- Table 6.15 Reset Input 294
- Figure 6.10 Interrupt Output 295
- Table 6.16 Interrupt Output 295
- • Target Timing 296
- • Initiator Timing 296
- • External Memory Timing 296
- 6.4.1 Target Timing 297
- 6-20 Specifications 302
- (Driven by LSI53C1000R) 305
- 6.4.2 Initiator Timing 306
- 6-40 Specifications 322
- 6.4.3 External Memory Timing 323
- 6-42 Specifications 324
- (Addr driven by LSI53C1000R; 325
- 6-44 Specifications 326
- 6-46 Specifications 328
- Cycle (Cont.) 331
- 6-52 Specifications 334
- (Addr Driven by LSI53C1000R 335
- 6-54 Specifications 336
- (Addr drvn by LSI53C1000R 339
- (Addr drvn by LSI53C1000R; 342
- 6.5 SCSI Timing Diagrams 344
- Quadrupled 40 MHz Clock 351
- 6-70 Specifications 352
- 6.6 Package Drawings 353
- 6-72 Specifications 354
- Package Drawings 6-73 355
- 6-78 Specifications 360
- Appendix A 361
- Register Summary 361
- (CSO) 0x53 Read Only 4-90 363
- A-8 Register Summary 368
- Appendix B 369
- External Memory Interface 369
- Diagram Examples 369
- IX-2 Index 374
- Index IX-3 375
- Numerics 376
- Index IX-5 377
- IX-6 Index 378
- Index IX-7 379
- IX-8 Index 380
- Index IX-9 381
- IX-10 Index 382
- Index IX-11 383
- IX-12 Index 384
- Index IX-13 385
- IX-14 Index 386
- Customer Feedback 387
Résumé du contenu
Page 1 - TECHNICAL
®DB14-000152-04LSI53C1000RPCI to Ultra160SCSI ControllerTECHNICALMANUALAugust 2003Version 2.2
Page 2
x ContentsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.4.1 Target Timing 6-156.4.2 Initiator Timing 6-246.4.3 Ext
Page 3 - Preface iii
3-6 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.3.2 Address and Data SignalsTable 3.3 describ
Page 4
PCI Bus Interface Signals 3-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.3.3 Interface Control SignalsTable 3.4
Page 5
3-8 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.3.4 Arbitration SignalsTable 3.5 describes th
Page 6
PCI Bus Interface Signals 3-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.3.5 Error Reporting SignalsTable 3.6 de
Page 7 - Contents
3-10 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.4 SCSI Bus Interface SignalsTable 3.8 contai
Page 8
SCSI Bus Interface Signals 3-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SDP[1:0]+ W1, P5 I/O SE:48 mASCSILVD:12
Page 9 - Contents ix
3-12 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 3.10 SCSI Control SignalsName11. LVD Mod
Page 10
General Purpose I/O (GPIO) Signals 3-13Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.5 General Purpose I/O (GPIO)
Page 11
3-14 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.6 Flash ROM and Memory Interface SignalsTabl
Page 12
Test Interface Signals 3-15Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.7 Test Interface SignalsTable 3.13 descri
Page 13
xiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figures1.1 Typical LSI53C1000R Board Application 1-21.2 Typical LSI5
Page 14
3-16 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.8 Power and Ground SignalsTable 3.14 describ
Page 15
MAD Bus Programming 3-17Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.9 MAD Bus ProgrammingThe MAD[7:0] pins, in a
Page 16
3-18 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.between the appropriate MAD[x] pin and VDD. Th
Page 17
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 4-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 18
4-2 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x00–0x01Vendor IDRead OnlyVID Vendor ID [15:0]
Page 19 - Introduction
PCI Configuration Registers 4-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x02–0x03Device IDRead OnlyDID
Page 20 - 1-2 Introduction
4-4 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved 5WIE Write and Invalidate Enable 4When this bi
Page 21 - General Description 1-3
PCI Configuration Registers 4-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x06–0x07StatusRead/WriteReads
Page 22 - 1.2 Benefits of Ultra160 SCSI
4-6 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.These bits are read only and indicate the slowest timetha
Page 23 - Technology
PCI Configuration Registers 4-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x09–0x0BClass Code (CC)Read O
Page 24 - 1.5 Benefits of TolerANT
xiiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.8 External Clock 6-116.9 Reset Input 6-126.10 Interrupt Output 6-
Page 25 - 1.6.1 SCSI Performance
4-8 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0DLatency Timer (LT)Read/WriteLT Latency Time
Page 26 - 1.6.2 PCI Performance
PCI Configuration Registers 4-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0FReservedThis register is r
Page 27 - 1.6.4 Ease of Use
4-10 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x18–0x1BBase Address Register Two (BAR2) (MEM
Page 28 - 1.6.5 Flexibility
PCI Configuration Registers 4-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x20–0x23Base Address Registe
Page 29 - 1.6.7 Testability
4-12 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2C–0x2DSubsystem Vendor ID (SVID)Read OnlySV
Page 30 - 1-12 Introduction
PCI Configuration Registers 4-13Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2E–0x2FSubsystem ID (SID)Re
Page 31 - Functional Description
4-14 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x30–0x33Expansion ROM Base Address (ERBA)Read
Page 32 - 8 Kbyte SCRIPTS RAM
PCI Configuration Registers 4-15Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x34Capabilities Pointer (CP)
Page 33 - 2.1.1 PCI Addressing
4-16 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x3CInterrupt Line (IL)Read/WriteIL Interrupt
Page 34 - 2-4 Functional Description
PCI Configuration Registers 4-17Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x3EMin_Gnt (MG)Read OnlyMG M
Page 35
xiiiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Cont.) 6-576.32 Slow M
Page 36 - 2-6 Functional Description
4-18 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x40Capability ID (CID)Read OnlyCID Capability
Page 37
PCI Configuration Registers 4-19Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.D2S D2_Support 10The LSI53C1000R sets t
Page 38 - 2-8 Functional Description
4-20 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DSCL Data_Scale [14:13]The LSI53C1000R does not support
Page 39 - • The following bits are set:
SCSI Registers 4-21Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x47DataRead OnlyDATA Data [7:0]This regi
Page 40 - 2-10 Functional Description
4-22 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 4.2 SCSI Register Map31 16 15 0 Address PageSCNTL3
Page 41 - 2.1.3 PCI Cache Mode
SCSI Registers 4-23Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x00SCSI Control Zero (SCNTL0)Read/WriteA
Page 42 - 2-12 Functional Description
4-24 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Full Arbitration, Selection/Reselection1. The LSI53C1000
Page 43
SCSI Registers 4-25Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.the arbitration sequence is complete. If a sequence
Page 44 - 2.1.3.5 Examples
4-26 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.can determine if it is necessary to send a CRC requestat
Page 45
SCSI Registers 4-27Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x01SCSI Control One (SCNTL1)Read/WriteR
Page 46
xivVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 47
4-28 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.CON Connected 4This bit is automatically set any time th
Page 48 - 2-18 Functional Description
SCSI Registers 4-29Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.An unexpected disconnect condition clears IARB with
Page 49 - 2.2.1 SCRIPTS Processor
4-30 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.expects a disconnect to occur, normally prior to sending
Page 50 - 2.2.2 Internal SCRIPTS RAM
SCSI Registers 4-31Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x03SCSI Control Three (SCNTL3)Read/Write
Page 51
4-32 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Message phases are not affected by this bit. BecauseUltr
Page 52 - 2-22 Functional Description
SCSI Registers 4-33Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Response ID Zero (RESPID0) andResponse ID One (RESP
Page 53
4-34 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x06SCSI Destination ID (SDID)Read/WriteR Rese
Page 54
SCSI Registers 4-35Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x07General Purpose (GPREG)Read/WriteA wr
Page 55
4-36 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x08SCSI First Byte Received (SFBR)Read/WriteS
Page 56 - 2-26 Functional Description
SCSI Registers 4-37Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x09SCSI Output Control Latch (SOCL)Read/
Page 57 - are set for
xvVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Tables2.1 PCI Bus Commands and Encoding Types 2-52.2 PCI Cache Mode
Page 58
4-38 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0ASCSI Selector ID (SSID)Read OnlyVAL SCSI V
Page 59
SCSI Registers 4-39Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.REQ Assert SCSI REQ/ Signal 7ACK Assert SCSI ACK/ S
Page 60 - 2-30 Functional Description
4-40 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.MDPE Master Data Parity Error 6This bit is set when the
Page 61
SCSI Registers 4-41Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• During a Transfer Control instruction, theCompare
Page 62 - • On every Store instruction
4-42 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x0DSCSI Status Zero (SSTAT0)Read OnlyILF SIDL
Page 63
SCSI Registers 4-43Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.WOA Won Arbitration 2When set, WOA indicates that t
Page 64 - 2.2.10 Parity/CRC/AIP Options
4-44 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.C_D SCSI C_D/ Signal 1This SCSI phase status bit is latc
Page 65
SCSI Registers 4-45Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved 4SPL1 Latched SCSI Parity for SD[15:8] 3
Page 66 - 2.2.11 DMA FIFO
4-46 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x10–0x13Data Structure Address (DSA)Read/Writ
Page 67 - 2.2.12 SCSI Data Paths
SCSI Registers 4-47Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.4. If the SCSI Interrupt Pending bit is set, read t
Page 68 - 2-38 Functional Description
xviVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.5 DIFFSENS SCSI Signals 6-46.6 Input Capacitance 6-46.7 8 mA Bidi
Page 69 - 2.2.13 SCSI Bus Interface
4-48 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.to notify an external processor of a predefined condition
Page 70 - 2-40 Functional Description
SCSI Registers 4-49Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• A SCSI gross error occurs• An unexpected disconne
Page 71 - 2.2.15 Synchronous Operation
4-50 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x15Interrupt Status One (ISTAT1)Read/WriteR R
Page 72
SCSI Registers 4-51Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x16Mailbox Zero (MBOX0)Read/WriteMBOX0 M
Page 73
4-52 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x18Chip Test Zero (CTEST0)Read/WriteFMT Byte
Page 74 - 2-44 Functional Description
SCSI Registers 4-53Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x1AChip Test Two (CTEST2)Read Only (bit
Page 75 - 2.2.16 Interrupt Handling
4-54 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.When it is set, MMWS contains bits [63:32] andSCRATCH B
Page 76 - 2-46 Functional Description
SCSI Registers 4-55Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.CLF Clear DMA FIFO 2When this bit is set, all data
Page 77
4-56 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x20ReservedThis register is reserved.Register
Page 78 - 2-48 Functional Description
SCSI Registers 4-57Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.registers. Each of the eight bytes that make up the
Page 79
xviiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.34 Normal/Fast Memory (≥ 128 Kbytes) Single Byte AccessWrite Cyc
Page 80 - 2-50 Functional Description
4-58 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved [5:3]BL2 Burst Length Bit 2 2This bit works w
Page 81 - before halting
SCSI Registers 4-59Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x24–0x26DMA Byte Counter (DBC)Read/Write
Page 82
4-60 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x27DMA Command (DCMD)Read/WriteDCMD DMA Comma
Page 83 - 2.2.17 Interrupt Routing
SCSI Registers 4-61Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x2C–0x2FDMA SCRIPTS Pointer (DSP)Read/Wr
Page 84 - 2-54 Functional Description
4-62 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x34–0x37Scratch Register A (SCRATCHA)Read/Wri
Page 85 - 2.2.18 Chained Block Moves
SCSI Registers 4-63Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.end-of-transfer cleanup and alignment, even if less
Page 86 - 2-56 Functional Description
4-64 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.This function is useful for memory-to-register operation
Page 87
SCSI Registers 4-65Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x39DMA Interrupt Enable (DIEN)Read/Write
Page 88 - 2.3 Parallel ROM Interface
4-66 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x3AScratch Byte Register (SBR)Read/WriteSBR S
Page 89
SCSI Registers 4-67Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.conditions are met), on writes to theDMA SCRIPTS Po
Page 90 - 2.4 Serial EEPROM Interface
xviiiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 91 - 2.5 Power Management
4-68 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.STD Start DMA Operation 2The LSI53C1000R fetches a SCSI
Page 92 - 2.5.2 Power State D1
SCSI Registers 4-69Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x3C–0x3FAdder Sum Output (ADDER)Read Onl
Page 93 - 2.5.4 Power State D3
4-70 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SEL Selected 5When set, this bit indicates the LSI53C100
Page 94 - 2-64 Functional Description
SCSI Registers 4-71Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.register. It can be accessed by setting bit 7, theE
Page 95 - Signal Descriptions
4-72 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SBMC SCSI Bus Mode Change 4Setting this bit allows the L
Page 96
SCSI Registers 4-73Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x42SCSI Interrupt Status Zero (SIST0)Rea
Page 97 - Signal Organization 3-3
4-74 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SEL Selected 5This bit is set when the LSI53C1000R is se
Page 98
SCSI Registers 4-75Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Note: Checking for this condition can be disabled b
Page 99 - 3.3 PCI Bus Interface Signals
4-76 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x43SCSI Interrupt Status One (SIST1)Read Only
Page 100
SCSI Registers 4-77Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x44ReservedThis register is reserved.Reg
Page 101
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 1-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 102 - 3.3.4 Arbitration Signals
4-78 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x47General Purpose Pin Control (GPCNTL)Read/W
Page 103 - 3.3.6 Interrupt Signals
SCSI Registers 4-79Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.GPIO[4:2] GPIO Enable [4:2]The general purpose cont
Page 104 - Table 3.9 SCSI Signals
4-80 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SEL[3:0] Selection Time-Out [3:0]These bits select the S
Page 105
SCSI Registers 4-81Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x49SCSI Timer One (STIME1)Read/WriteR Re
Page 106
4-82 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.HTHSF Handshake to Handshake Timer Scale Factor 4Setting
Page 107 - Table 3.11 GPIO Signals
SCSI Registers 4-83Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4BResponse ID One (RESPID1)Read/WriteRE
Page 108
4-84 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SLT Selection Response Logic Test 3This bit is set when
Page 109 - 3.7 Test Interface Signals
SCSI Registers 4-85Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4DSCSI Test One (STEST1)Read/WriteR Res
Page 110 - 3.8 Power and Ground Signals
4-86 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x4ESCSI Test Two (STEST2)Read/WriteSCE SCSI C
Page 111 - 3.9 MAD Bus Programming
SCSI Registers 4-87Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved [5:4]SZM SCSI High Impedance Mode 3Setti
Page 112
iiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.This document contains proprietary information of LSI Logic Corporat
Page 113 - Registers
1-2 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.configuration and automatically tests and adjusts the S
Page 114 - Registers:0x00–0x01
4-88 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved 6HSC Halt SCSI Clock 5Asserting this bit caus
Page 115 - Registers:0x04–0x05
SCSI Registers 4-89Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0x50–0x51SCSI Input Data Latch (SIDL)Read
Page 116 - 4-4 Registers
4-90 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved [5:0]Register: 0x53Current Inbound SCSI Offse
Page 117 - Registers:0x06–0x07
SCSI Registers 4-91Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.asynchronous mode. It also writes to the synchronou
Page 118 - Register: 0x08
4-92 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.phase referred to here is the phase encoded in the block
Page 119 - Register: 0x0C
SCSI Registers 4-93Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x57Chip Control One (CCNTL1)Read/WritePU
Page 120 - Register: 0x0E
4-94 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DMA Next Address 64 (DNAD64) to provide 40-bitaddressing
Page 121 - Registers:0x14–0x17
SCSI Registers 4-95Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.receiving data using programmed I/O. This register
Page 122 - Registers:0x1C–0x1F
4-96 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DSKEW[1:0] Setup Data Skew Control [3:2]These bits contr
Page 123 - Registers:0x28–0x2B
SCSI Registers 4-97Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Base Address Register Three (BAR3) (SCRIPTS RAM).In
Page 124 - Registers:0x2C–0x2D
General Description 1-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.solving the protocol overhead problems of previ
Page 125 - Registers:0x2E–0x2F
4-98 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xA4–0xA7Memory Move Write Selector (MMWS)Read
Page 126 - Registers:0x30–0x33
SCSI Registers 4-99Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Writes to the SCRIPT Fetch Selector (SFS) register
Page 127 - Registers:0x38–0x3B
4-100 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xB4–0xB7Dynamic Block Move Selector (DBMS)Re
Page 128 - Register: 0x3D
SCSI Registers 4-101Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0xBCSCSI Control Four (SCNTL4)Read/Write
Page 129 - Register: 0x3F
4-102 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.XCLKH_ST Extra Clock of Data Hold on ST Transfer Edge 2
Page 130 - Registers:0x42–0x43
SCSI Registers 4-103Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Note: The receive rate is independent of the setti
Page 131 - Registers:0x44–0x45
4-104 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 4.1 Single Transition Transfer WaveformsCLK1REQ/
Page 132 - Register: 0x46
SCSI Registers 4-105Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 4.2 DT Transfer Waveforms (XCLKS Examples)C
Page 133 - 4.2 SCSI Registers
4-106 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 4.3 DT Transfer Waveforms (XCLKH Examples)CLK1RE
Page 134 - Table 4.2 SCSI Register Map
SCSI Registers 4-107Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 4.4 DT Transfer RatesClock(MHz) DivisorNumbe
Page 135 - Register: 0x00
1-4 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.1.2 Benefits of Ultra160 SCSIUltra160 SCSI delivers dat
Page 136 - 4-24 Registers
4-108 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.160 4 0 25.00 20.00 20.00160 4 1 25.00 20.00 16.00160 4
Page 137 - SCSI Registers 4-25
SCSI Registers 4-109Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.40 1.5 0 37.50 13.33 13.3340 1.5 1 37.50 13.33 10.
Page 138 - 4-26 Registers
4-110 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.40 4 4 100.00 5.00 2.5040 8 0 200.00 2.50 2.5040 8 1 20
Page 139 - Register: 0x01
SCSI Registers 4-111Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.160 3 1 18.75 13.33 10.67160 3 2 18.75 13.33 8.891
Page 140 - 4-28 Registers
4-112 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.40 3 0 75.00 3.33 3.3340 3 1 75.00 3.33 2.6740 3 2 75.0
Page 141 - Register: 0x02
SCSI Registers 4-113Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0xBDReservedThis register is reserved.Re
Page 142 - 4-30 Registers
4-114 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.PARITYERR Parity Error Status 0This bit represents the
Page 143 - Register: 0x03
SCSI Registers 4-115Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xC0–0xC3Phase Mismatch Jump Address One
Page 144 - Register: 0x04
4-116 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xC8–0xCBRemaining Byte Count (RBC)Read/Write
Page 145 - Register: 0x05
SCSI Registers 4-117Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xCC–0xCFUpdated Address (UA)Read/WriteU
Page 146 - Register: 0x06
Benefits of SURElink (Ultra160 SCSI Domain Validation) Technology 1-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.1.
Page 147 - Register: 0x07
4-118 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xD0–0xD3Entry Storage Address (ESA)Read/Writ
Page 148
SCSI Registers 4-119Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xD4–0xD7Instruction Address (IA)Read/Wr
Page 149 - Register: 0x09
4-120 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0xDBReservedThis register is reserved.Registe
Page 150 - Register: 0x0B
SCSI Registers 4-121Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0xE2CRC Control Zero (CRCCNTL0)Read/Writ
Page 151
4-122 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved 6ENAS Enable CRC Auto Seed 5Setting this bit
Page 152 - 4-40 Registers
SCSI Registers 4-123Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.CRCD CRC Data [31:0]If CRCDSEL = 0b00, this regist
Page 153 - SCSI Registers 4-41
4-124 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xF0–0xF1DMA FIFO Byte Count (DFBC)Read OnlyD
Page 154
SCSI Shadow Registers 4-125Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.4.3 SCSI Shadow RegistersNote: For more inf
Page 155
4-126 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Register: 0x42Shadowed SCSI SGE Status 0Read/WriteThis
Page 156
SCSI Shadow Registers 4-127Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.register is shadowed behind the SCSI Interr
Page 157 - SCSI Registers 4-45
1-6 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.allows a longer SCSI cable and more devices on the bus
Page 158 - Register: 0x14
4-128 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xA0–0xA3Shadowed Memory Move Read Selector (
Page 159 - SCSI Registers 4-47
SCSI Shadow Registers 4-129Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Registers:0xA8–0xABShadowed SCRIPT Fetch Se
Page 160 - • The LSI53C1000R is selected
4-130 RegistersVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 161 - SCSI Registers 4-49
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 5-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 162 - Register: 0x15
5-2 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.When an interrupt is generated, the LS
Page 163 - Register: 0x17
SCSI SCRIPTS 5-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• The host CPU, through programmed I/O, gives theDMA S
Page 164 - Register: 0x19
5-4 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 5.1 SCRIPTS Overview5.2 Block M
Page 165 - Register: 0x1A
Block Move Instructions 5-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 5.2 Block Move Instruction – First D
Page 166 - Register: 0x1B
5-6 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.IndirectWhen set, the 32-bit user data
Page 167
Block Move Instructions 5-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.generate the physical address that fetches
Page 168 - Register: 0x21
Summary of LSI53C1000R Benefits 1-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.1.6 Summary of LSI53C1000R BenefitsTh
Page 169 - Register: 0x22
5-8 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.64-Bit AddressingIf the Enable 64-bit
Page 170 - Register: 0x23
Block Move Instructions 5-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table Indirect Index mode mapping:EN64TIBMV
Page 171 - Registers:0x24–0x26
5-10 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.OPC Opcode 27This 1-bit field defines t
Page 172 - Register: 0x27
Block Move Instructions 5-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.the LSI53C1000R stores the last byte in th
Page 173 - Registers:0x2C–0x2F
5-12 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If the SCSI phase bits do not match t
Page 174 - Register: 0x38
Block Move Instructions 5-13Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.TC[23:0] Transfer Counter [23:0]This 24-bi
Page 175
5-14 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.2.3 Third DwordThis section describ
Page 176 - 4-64 Registers
I/O Instructions 5-15Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Target ModeReselect InstructionThe LSI53C1000R ar
Page 177 - Register: 0x39
5-16 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If reselected, the LSI53C1000R fetche
Page 178 - Register: 0x3B
I/O Instructions 5-17Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Initiator ModeSelect InstructionThe LSI53C1000R a
Page 179 - SCSI Registers 4-67
1-8 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• Supports variable block size and scatter/gather data
Page 180 - 4-68 Registers
5-18 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Wait Reselect InstructionIf the LSI53
Page 181 - Registers:0x3C–0x3F
I/O Instructions 5-19Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.TI Table Indirect Mode 25When this bit is set, th
Page 182 - 4-70 Registers
5-20 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DirectUses the device ID and physical
Page 183
I/O Instructions 5-21Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved [23:20]ENDID[3:0] Encoded SCSI Destina
Page 184 - 4-72 Registers
5-22 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.R Reserved [5:4]ATN Set/Clear SATN/ 3
Page 185 - Register: 0x42
Read/Write Instructions 5-23Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.4 Read/Write InstructionsThe Read/Write
Page 186 - 4-74 Registers
5-24 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.A[6:0] Register Address – A[6:0] [22:
Page 187 - • A SCRIPTS RAM parity error
Read/Write Instructions 5-25Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.(subtrahend) with 0xFF, and add 1 to the r
Page 188 - Register: 0x43
5-26 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.011 XOR data with register andplace t
Page 189 - Register: 0x45
Transfer Control Instructions 5-27Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.5 Transfer Control InstructionsThi
Page 190 - Register: 0x47
Summary of LSI53C1000R Benefits 1-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• Prefetches up to 8 Dwords of SCRIP
Page 191 - Register: 0x48
5-28 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.the DMA SCRIPTS Pointer (DSP) registe
Page 192
Transfer Control Instructions 5-29Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.When a Return instruction is execute
Page 193 - Register: 0x49
5-30 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.driven on the SCSI bus. The following
Page 194 - Register: 0x4A
Transfer Control Instructions 5-31Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The SCRIPTS program counter is a 32-
Page 195 - Register: 0x4C
5-32 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.CD Compare Data 18When this bit is se
Page 196 - 4-84 Registers
Transfer Control Instructions 5-33Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DC Data Compare Value [7:0]This 8-bi
Page 197 - Register: 0x4D
5-34 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.6 Memory Move InstructionsFor Memor
Page 198 - Register: 0x4E
Memory Move Instructions 5-35Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 5.12 Memory Move Instructions – Fi
Page 199 - Register: 0x4F
5-36 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The SCSI First Byte Received (SFBR) i
Page 200 - 4-88 Registers
Load and Store Instructions 5-37Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.6.3 Third DwordThis section describe
Page 201 - Register: 0x52
1-10 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• Maskable and pollable interrupts.• Wide SCSI, A or
Page 202 - Registers:0x54–0x55
5-38 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.A maximum of 4 bytes may be moved wit
Page 203 - Register: 0x56
Load and Store Instructions 5-39Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.5.7.1 First DwordThis section describe
Page 204 - 4-92 Registers
5-40 SCSI SCRIPTS Instruction SetVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.A[7:0] Register Address [23:16]A[7:0]
Page 205 - Register: 0x57
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 6-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 206 - Registers:0x58–0x59
6-2 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.1 Absolute Maximum Stress RatingsSymbol Param
Page 207 - Register: 0x5B
DC Characteristics 6-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.1 LVD DriverTable 6.3 LVD Driver SCSI S
Page 208 - Registers:0x5C–0x5F
6-4 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.2 LVD ReceiverVCM+−++−−VI2VI2+−Table 6.5 DIF
Page 209 - Registers:0xA0–0xA3
DC Characteristics 6-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.7 8 mA Bidirectional Signals – GPIO0_FET
Page 210 - Registers:0xA8–0xAB
6-6 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.10 8 mA PCI Bidirectional Signals – AD[63:0],
Page 211 - Registers:0xB0–0xB3
TolerANT Technology Electrical Characteristics 6-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.2 TolerANT Technol
Page 212 - Registers:0xB8–0xBB
Summary of LSI53C1000R Benefits 1-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.1.6.6 ReliabilityThe following feat
Page 213 - Register: 0xBC
6-8 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.3 Rise and Fall Time Test ConditionFigure 6.
Page 214 - SCF Divisor 2×
TolerANT Technology Electrical Characteristics 6-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.5 Hysteresi
Page 215
6-10 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.7 Output Current as a Function of Output Vo
Page 216 - 4-104 Registers
AC Characteristics 6-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.3 AC CharacteristicsThe AC characteristics de
Page 217 - SCSI Registers 4-105
6-12 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.15 and Figure 6.9 provide Reset Input timing
Page 218 - 4-106 Registers
AC Characteristics 6-13Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.16 and Figure 6.10 provide Interrupt Ou
Page 219 - Table 4.4 DT Transfer Rates
6-14 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.4 PCI and External Memory Interface Timing Diagram
Page 220
PCI and External Memory Interface Timing Diagrams 6-15Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.– Normal/Fast Me
Page 221
6-16 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.11 PCI Configuration Register ReadTable 6.17
Page 222
PCI and External Memory Interface Timing Diagrams 6-17Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.12 PCI
Page 223
Preface iiiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.PrefaceThis book is the primary reference and technical man
Page 224
1-12 IntroductionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 225 - Register: 0xBE
6-18 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.13 Operating Registers/SCRIPTS RAM Read, 32
Page 226 - Register: 0xBF
PCI and External Memory Interface Timing Diagrams 6-19Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.20 Opera
Page 227 - Registers:0xC4–0xC7
6-20 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.14 Operating Register/SCRIPTS RAM Read, 64
Page 228 - Registers:0xC8–0xCB
PCI and External Memory Interface Timing Diagrams 6-21Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.15 Oper
Page 229 - Registers:0xCC–0xCF
6-22 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.22 Operating Register/SCRIPTS RAM Write, 64
Page 230 - Registers:0xD0–0xD3
PCI and External Memory Interface Timing Diagrams 6-23Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.16 Oper
Page 231 - Registers:0xD8–0xDA
6-24 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.4.2 Initiator TimingTables 6.23 through 6.30 and f
Page 232 - Registers:0xE0–0xE1
PCI and External Memory Interface Timing Diagrams 6-25Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.17 Nonb
Page 233 - Register: 0xE3
6-26 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.24 Burst Opcode Fetch, 32-Bit Address and Da
Page 234 - Registers:0xE4–0xE7
PCI and External Memory Interface Timing Diagrams 6-27Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.18 Burs
Page 235 - Registers:0xE8–0xEF
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 2-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 236 - Registers:0xF4–0xFF
6-28 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.25 Back to Back Read, 32-Bit Address and Dat
Page 237 - 4.3 SCSI Shadow Registers
PCI and External Memory Interface Timing Diagrams 6-29Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.19 Back
Page 238
6-30 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.26 Back to Back Write, 32-Bit Address and Da
Page 239
PCI and External Memory Interface Timing Diagrams 6-31Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.20 Back
Page 240
6-32 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.27 Burst Read, 32-Bit Address and DataSymbol
Page 241
PCI and External Memory Interface Timing Diagrams 6-33Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.21 Burs
Page 242 - 4-130 Registers
6-34 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.28 Burst Read, 64-Bit Address and DataSymbol
Page 243 - SCSI SCRIPTS Instruction Set
PCI and External Memory Interface Timing Diagrams 6-35Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.22 Burs
Page 244
6-36 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.29 Burst Write, 32-Bit Address and DataSymbo
Page 245 - SCSI SCRIPTS 5-3
PCI and External Memory Interface Timing Diagrams 6-37Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.23 Burs
Page 246 - 5.2 Block Move Instructions
2-2 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 2.1 LSI53C1000R Block DiagramThe LSI5
Page 247 - Lower Dword Address of Data
6-38 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.30 Burst Write, 64-Bit Address and DataSymbo
Page 248 - Address of Pointer to Data
PCI and External Memory Interface Timing Diagrams 6-39Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.24 Burs
Page 249 - Physical Data Address
6-40 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 250
PCI and External Memory Interface Timing Diagrams 6-41Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.4.3 External M
Page 251
6-42 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.25 External Memory ReadCLK(Driven by System
Page 252 - 1 CHMOV/CHMOV64
PCI and External Memory Interface Timing Diagrams 6-43Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.25 Exte
Page 253 - 1 MOVE/MOVE64
6-44 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 254
PCI and External Memory Interface Timing Diagrams 6-45Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.32 Exter
Page 255 - 5.2.2 Second Dword
6-46 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.26 External Memory WriteCLK(Driven by Syste
Page 256 - 5.3 I/O Instructions
PCI and External Memory Interface Timing Diagrams 6-47Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.26 Exte
Page 257
PCI Functional Description 2-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1 PCI Functional DescriptionThe LSI53C
Page 258
6-48 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.33 Normal/Fast Memory (≥ 128 Kbytes) Single
Page 259
PCI and External Memory Interface Timing Diagrams 6-49Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.27 Norm
Page 260
6-50 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.34 Normal/Fast Memory (≥ 128 Kbytes) Single
Page 261 - Config ID Offset/period 00
PCI and External Memory Interface Timing Diagrams 6-51Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.28 Norm
Page 262 - Command Table Offset
6-52 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.29 Normal/Fast Memory (≥ 128 Kbytes) Multip
Page 263
PCI and External Memory Interface Timing Diagrams 6-53Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.29 Norm
Page 264 - 5.3.2 Second Dword
6-54 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.30 Normal/Fast Memory (≥ 128 Kbytes) Multip
Page 265 - 5.4 Read/Write Instructions
PCI and External Memory Interface Timing Diagrams 6-55Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.30 Norm
Page 266 - 5.4.2 Second Dword
6-56 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.35 Slow Memory (≥ 128 Kbytes) Read CycleSymb
Page 267
PCI and External Memory Interface Timing Diagrams 6-57Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.31 Slow
Page 268
2-4 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.1.2 I/O SpaceThe PCI specification defines
Page 269 - 5.5.1 First Dword
6-58 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.36 Slow Memory (≥ 128 Kbytes) Write CycleSym
Page 270
PCI and External Memory Interface Timing Diagrams 6-59Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.32 Slow
Page 271
6-60 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.33 ≤ 64 Kbytes ROM Read CycleTable 6.37 ≤ 6
Page 272 - MSG C/D I/O SCSI Phase
PCI and External Memory Interface Timing Diagrams 6-61Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.34 ≤ 64
Page 273
6-62 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.5 SCSI Timing DiagramsTables 6.39 through 6.50 and
Page 274
SCSI Timing Diagrams 6-63Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.36 Initiator Asynchronous ReceiveFig
Page 275 - 5.5.3 Third Dword
6-64 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.38 Target Asynchronous ReceiveTable 6.42 Ta
Page 276 - 5.6 Memory Move Instructions
SCSI Timing Diagrams 6-65Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.44 SCSI-2 Fast Transfers 10.0 Mbytes
Page 277 - Memory Move Instructions 5-35
6-66 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.39 Initiator and Target ST Synchronous Tran
Page 278 - 5.6.2 Second Dword
SCSI Timing Diagrams 6-67Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes
Page 279 - 5.6.3 Third Dword
PCI Functional Description 2-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.2.1 Interrupt Acknowledge CommandThe
Page 280
6-68 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.tDT5Receive data setup to SREQ/ transition 5 – nstDT
Page 281 - 5.7.1 First Dword
SCSI Timing Diagrams 6-69Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.40 Initiator and Target DT Synchrono
Page 282 - 5.7.2 Second Dword
6-70 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 283 - Specifications
Package Drawings 6-71Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.6.6 Package DrawingsFigure 6.41 illustrates the s
Page 284
6-72 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.41 LSI53C1000R 456 BGA Chip – Top ViewA1 A2
Page 285
Package Drawings 6-73Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.41 LSI53C1000R 456 BGA Chip – Top View (
Page 286 - Table 6.6 Input Capacitance
6-74 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.51 Alphanumeric List by Signal NameACK64/ AB
Page 287 - , MWE/, TDO
Package Drawings 6-75Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.51 Alphanumeric List by Signal Name (Cont
Page 288
6-76 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.52 Alphanumeric List by BGA PositionA1 VDD_I
Page 289
Package Drawings 6-77Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table 6.52 Alphanumeric List by BGA Position (Con
Page 290
2-6 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.2.3 I/O Read CommandThe LSI53C1000R uses
Page 291
6-78 SpecificationsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 6.42 LSI53C1000R 456 BGA Mechanical DrawingIm
Page 292 - 6-10 Specifications
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual A-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Append
Page 293 - 6.3 AC Characteristics
A-2 Register SummaryVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Latency Timer (LT) 0x0D Read/Write 4-8Max_Lat (ML)
Page 294 - Table 6.15 Reset Input
A-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Table A.2 lists the LSI53C1000R SCSI registers, Phase Mismatch Jump
Page 295 - Table 6.16 Interrupt Output
A-4 Register SummaryVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.DMA Next Address 64 (DNAD64) 0xB8–0xBB Read/Write
Page 296 - • External Memory Timing
A-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SCSI Bus Control Lines (SBCL) 0x0B Read Only 4-38SCSI Bus Data Line
Page 297 - 6.4.1 Target Timing
A-6 Register SummaryVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.SCSI Test Zero (STEST0) 0x4C Read Only 4-83SCSI Ti
Page 298
A-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Shadow RegistersShadowed Memory Move Read Selector (MMRS) 0xA0–0xA3
Page 299
A-8 Register SummaryVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 300
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual B-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Append
Page 301
PCI Functional Description 2-7Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.2.9 Configuration Write CommandThe Co
Page 302 - 6-20 Specifications
B-2 External Memory Interface Diagram ExamplesVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure B.2 64 Kbyte Inte
Page 303
B-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Mem
Page 304
B-4 External Memory Interface Diagram ExamplesVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure B.4 512 Kbyte Int
Page 305 - (Driven by LSI53C1000R)
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual IX-1IndexSymbols(64TIMOD) 4-93(A) 5-21(A[6:0]) 5-24(A[7:0]) 5-40(A7) 5-24(AAP) 4-26(ABRT)
Page 306 - 6.4.2 Initiator Timing
IX-2 Index(DPE) 4-5(DPR) 4-6(DRS) 4-99(DSA) 4-46, 5-39(DSCL) 4-20(DSI) 4-19, 4-88(DSLT) 4-20(DSP) 4-61(DSPS) 4-61(DSTAT) 4-39(DT[1:0]) 4-5(EBM) 4-4(EI
Page 307
Index IX-3(PMCSR) 4-19(PMCSR_BSE) 4-20(PMEC) 4-19(PMES) 4-18(PMJAD1) 4-115(PMJAD2) 4-115(PMJCTL) 4-91(PST) 4-19(PWS[1:0]) 4-20(QEN) 4-85(QSEL) 4-85(RA
Page 308
IX-4 Index(VP) 5-32(VUE0) 4-30(VUE1) 4-30(WATN) 4-25(WIE) 4-4(WOA) 4-43(WRIE) 4-55(WSR) 4-30(WSS) 4-30Numerics32/64-bit jump 5-3132-bit addressing 5-6
Page 309
Index IX-5burstlength (BL[1:0]) 4-62length bit 2 (BL2) 4-58opcode fetch enable (BOF) 4-64size selection 2-7burst opcode fetch 32-bit address and data
Page 310
IX-6 IndexDIEN 2-48differential mode 2-39DIP 2-51direct 5-20disableauto FIFO clear (DISFC) 4-92CRC checking 4-121CRC protocol checking 4-121dual addre
Page 311
Index IX-7flush DMA FIFO (FLF) 4-54flushing (FLSH) 4-50FRAME/ 3-7full arbitration, selection/reselection 4-24function complete(CMP) 4-69, 4-73Ggeneral
Page 312
2-8 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.size based on the amount of data to transfer
Page 313
IX-8 Indexon the fly 5-31on the fly (INTF) 4-48on the fly instruction 5-29output 6-13pin (IP[7:0]) 4-16polling 2-46registers 2-46DIEN 2-48DSTAT 2-48IS
Page 314
Index IX-9read multiple 2-12, 2-13read multiple command 2-7space 2-3, 2-4to memory 2-18to memory moves 2-18write 2-12, 2-13write and invalidate 2-12wr
Page 315
IX-10 Indexcapabilities 4-18control/status 4-19stateD0 2-62D1 2-62D2 2-63D3 2-63state (PWS[1:0]) 4-20prefetchenable (PFEN) 4-66flush 2-32flush (PFF) 4
Page 316
Index IX-11instruction type 5-14opcode 5-14relative addressing mode 5-18select with ATN/ 5-20set/clear carry 5-21set/clear SACK/ 5-21set/clear SATN/ 5
Page 317
IX-12 Indexblock move 5-4I/O 5-14read/write 5-23interface signals 3-10interrupt 2-51enable one (SIEN1) 2-48, 4-71enable zero (SIEN0) 2-35, 2-48, 4-69s
Page 318
Index IX-13SIP 2-50, 2-51SIST0 2-47SIST1 2-47slow memoryread cycle 6-56write cycle 6-58slow ROM pin 3-18SODLleast significant byte full (OLF) 4-42most
Page 319
IX-14 IndexUltra2 SCSItransfers 6-66, 6-68unexpected disconnect (UDC) 4-71, 4-75updated address (UA) 4-117upper register address line (A7) 5-24use dat
Page 320
LSI53C1000R PCI to Ultra160 SCSI Controller Technical ManualVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Customer F
Page 321
Customer FeedbackVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Reader’s CommentsFax your comments to: LSI Logic Corp
Page 322 - 6-40 Specifications
PCI Functional Description 2-9Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Read Multiple with Read Line Enabled – W
Page 323 - 6.4.3 External Memory Timing
iv PrefaceVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• Appendix B, External Memory Interface Diagram Examples,con
Page 324 - 6-42 Specifications
2-10 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Multiple Cache Line Transfers – The Memory
Page 325 - (Addr driven by LSI53C1000R;
PCI Functional Description 2-11Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.3 PCI Cache ModeThe LSI53C1000R sup
Page 326 - 6-44 Specifications
2-12 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.3.1 Enabling Cache ModeTo enable the ca
Page 327
PCI Functional Description 2-13Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If the corresponding cache command is n
Page 328 - 6-46 Specifications
2-14 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.3.5 ExamplesThe examples in this sectio
Page 329
PCI Functional Description 2-15Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Read Example 2 – Burst = 8 Dwords; Cach
Page 330
2-16 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Write Example 1 – Burst = 4 Dwords; Cache L
Page 331 - Cycle (Cont.)
PCI Functional Description 2-17Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Write Example 2 – Burst = 8 Dwords; Cac
Page 332
2-18 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.1.3.6 Memory-to-Memory MovesMemory-to-Mem
Page 333
SCSI Functional Description 2-19Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.1 SCRIPTS ProcessorThe SCSI SCRIPT
Page 334 - 6-52 Specifications
Preface vVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.LSI Logic World Wide Web Home Pagewww.lsil.comSCSI SCRIPTS™ P
Page 335 - (Addr Driven by LSI53C1000R
2-20 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.2 Internal SCRIPTS RAMThe LSI53C1000R h
Page 336 - 6-54 Specifications
SCSI Functional Description 2-21Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.3 64-Bit Addressing in SCRIPTSThe
Page 337
2-22 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.completed a selection or when it has succes
Page 338
SCSI Functional Description 2-23Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If the commands complete successfully
Page 339 - (Addr drvn by LSI53C1000R
2-24 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.5.2 Parallel Protocol RequestCRC, Sync/
Page 340
SCSI Functional Description 2-25Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Note: For DT mode or when the Protocol
Page 341
2-26 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The AIP error status and the live AIP code
Page 342 - (Addr drvn by LSI53C1000R;
SCSI Functional Description 2-27Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• The SCSI Control Three (SCNTL3) regi
Page 343
2-28 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• The SCSI Control Four (SCNTL4) register:–
Page 344 - 6.5 SCSI Timing Diagrams
SCSI Functional Description 2-29Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• The AIP Control One (AIPCNTL1) regis
Page 345
vi PrefaceVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 346
2-30 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• The CRC Control One (CRCCNTL1) register:–
Page 347
SCSI Functional Description 2-31Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.5.5 Using the SCSI Clock Quadruple
Page 348
2-32 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.To ensure the LSI53C1000R always operates f
Page 349
SCSI Functional Description 2-33Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Note: This feature is only useful if P
Page 350
2-34 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.10 Parity/CRC/AIP OptionsThe LSI53C1000
Page 351 - Quadrupled 40 MHz Clock
SCSI Functional Description 2-35Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Enable Parity/CRC/AIPError InterruptSC
Page 352 - 6-70 Specifications
2-36 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.11 DMA FIFOThe DMA FIFO is 8 bytes wide
Page 353 - 6.6 Package Drawings
SCSI Functional Description 2-37Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The LSI53C1000R supports 64-bit memory
Page 354 - 6-72 Specifications
2-38 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.in the SODL register contains data. If bit
Page 355 - Package Drawings 6-73
SCSI Functional Description 2-39Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.12.4 Synchronous SCSI ReceiveWhen
Page 356
Contents viiVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.ContentsChapter 1 Introduction1.1 General Description 1-11
Page 357
2-40 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.(or active) termination is recommended. Fig
Page 358
SCSI Functional Description 2-41Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.14 Select/Reselect during Selectio
Page 359
2-42 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.15.1 SCSI Control Three (SCNTL3) Regist
Page 360 - 6-78 Specifications
SCSI Functional Description 2-43Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Bit 2, XCLKH_ST (Extra Clock of Data H
Page 361 - Register Summary
2-44 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.To configure the LSI53C1000R for Ultra160 DT
Page 362
SCSI Functional Description 2-45Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 2.5 Determining the Synchronous
Page 363 - (CSO) 0x53 Read Only 4-90
2-46 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.16.1 Polling and Hardware InterruptsThe
Page 364
SCSI Functional Description 2-47Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If the DIP bit in the Interrupt Status
Page 365
2-48 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.CLF (Clear DMA FIFO) and CSF (Clear SCSI FI
Page 366
SCSI Functional Description 2-49Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Some SCSI interrupts are nonfatal. The
Page 367
viii ContentsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.8 Load and Store Instructions 2-332.2.9 JTAG Boundary
Page 368 - A-8 Register Summary
2-50 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.If a fatal interrupt occurs while masked, S
Page 369 - Diagram Examples
SCSI Functional Description 2-51Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.INTA/ pin. Because no interrupt is gen
Page 370
2-52 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.• In the case of Transfer Control Instructi
Page 371
SCSI Functional Description 2-53Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.17 Interrupt RoutingThis section d
Page 372
2-54 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 2.6 Interrupt Routing Hardware Using
Page 373
SCSI Functional Description 2-55Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.18 Chained Block MovesBecause the
Page 374 - IX-2 Index
2-56 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.2.18.1 Wide SCSI Send BitThe WSS bit is s
Page 375 - Index IX-3
SCSI Functional Description 2-57Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.transfer. Performing either a SCSI sen
Page 376 - Numerics
2-58 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.instruction is executed, the data transfer
Page 377 - Index IX-5
Parallel ROM Interface 2-59Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The LSI53C1000R supports a variety of sizes
Page 378 - IX-6 Index
Contents ixVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapter 4 Registers4.1 PCI Configuration Registers 4-14.2 SC
Page 379 - Index IX-7
2-60 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.4 Serial EEPROM InterfaceThe LSI53C1000R
Page 380 - IX-8 Index
Power Management 2-61Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.4.2 No Download ModeWhen MAD[7] is pulled up th
Page 381 - Index IX-9
2-62 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The LSI53C1000R power states are independen
Page 382 - IX-10 Index
Power Management 2-63Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.2.5.3 Power State D2Power state D2 is a lower pow
Page 383 - Index IX-11
2-64 Functional DescriptionVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Page 384 - IX-12 Index
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 3-1Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Chapte
Page 385 - Index IX-13
3-2 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.The PCI Interface contains several functional g
Page 386 - IX-14 Index
Signal Organization 3-3Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.Figure 3.1 LSI53C1000R Signal GroupingCLKRST/AD
Page 387 - Customer Feedback
3-4 Signal DescriptionsVersion 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.2 Internal Pull-ups and Pull-downsSeveral LSI
Page 388
PCI Bus Interface Signals 3-5Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.3.3 PCI Bus Interface SignalsThe PCI Bus
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